Patents by Inventor Takatsugu Kusumi

Takatsugu Kusumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8779478
    Abstract: A TFT 20 includes a gate electrode 21, a gate insulating film 22, a semiconductor layer 23, a source electrode 24, a drain electrode 25, etc. The semiconductor layer 23 is comprised of a metal oxide semiconductor (IGZO), and has a source portion 23a that contacts the source electrode 24, a drain electrode 23b that contacts the drain electrode 25, and a channel portion 23c that is located between the source and drain portions 23a, 23b. A reduced region 30 is formed at least in the channel portion 23c of the semiconductor layer 23, and the reduced region 30 has a higher content of a simple substance of a metal such as In than the remaining portion of the semiconductor layer 23.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: July 15, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masao Moriguchi, Michiko Takei, Yohsuke Kanzaki, Tsuyoshi Inoue, Tetsuo Fukaya, Yudai Takanishi, Takatsugu Kusumi, Yoshiki Nakatani, Tetsuya Okamoto, Kenji Nakanishi
  • Publication number: 20140110249
    Abstract: The purpose of the present invention is to provide a sputtering target with which a film having excellent characteristics can be obtained. A sputtering target (100) is constituted of a plurality of target members (10), a backing plate (20), a bonding agent (30), and protective members (50). The plurality of target members (10) and the backing plate (20) are bonded to each other with the bonding agent (30) therebetween. On a backing plate (20) surface that corresponds in position to gaps (15) between adjacent target members (10), grooves (40) are formed. Each of the grooves (40) is provided with the protective members (50), which are composed of the same material as that of the target members (10). The width (W2) of the protective members (50) is greater than the width (W1) of the gaps (15), and is less than the width (W3) of the grooves (40). The thickness (T4) of the protective members (50) is larger than the depth (D1) of the grooves (40).
    Type: Application
    Filed: February 24, 2012
    Publication date: April 24, 2014
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yohsuke Kanzaki, Takatsugu Kusumi, Naohiro Tamari, Masao Moriguchi
  • Publication number: 20140103342
    Abstract: A method of manufacturing a TFT substrate includes: forming a gate electrode (12) and a gate insulating film (30) on a substrate (8); forming a source electrode (14) and a drain electrode (15) at a gap from each other on the gate insulating film (30), and forming a drain connection part (16); forming, after the step of forming the source electrode and the drain electrode, an oxide semiconductor layer (18, 18a, 18b) that contains a channel portion connecting the source electrode (14) to the drain electrode (15) and that contains an additional portion (18a) covering the drain connection part (16); oxidizing a surface of the oxide semiconductor layer (18, 18a, 18b); forming a contact hole (22) in an insulating film (32) that covers the oxide semiconductor layer; removing a portion of the additional portion (18a) of the oxide semiconductor layer that is located inside the contact hole (22); and forming a conductive layer (20) that electrically connects the drain connection part (16) that has been exposed.
    Type: Application
    Filed: May 29, 2012
    Publication date: April 17, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yudai Takanishi, Masao Moriguchi, Yohsuke Kanzaki, Takatsugu Kusumi
  • Publication number: 20140034947
    Abstract: A thin film transistor includes a gate electrode (11a), a gate insulating film (12a) covering the gate electrode (11a), a semiconductor layer (13a) made of an oxide semiconductor and provided on the gate insulating film (12a), a source electrode (16aa) and a drain electrode (16ab) provided on the semiconductor layer (13a) via easily reducible metal layers (15aa, 15ab) and spaced apart from each other, with a channel region (C) interposed therebetween, a conductive region (E) provided in the semiconductor layer (13a), and a diffusion reducing portion (13ca, 13cb) provided in the semiconductor layer (13a), for reducing diffusion of the conductive region (E) into the channel region (C).
    Type: Application
    Filed: April 12, 2012
    Publication date: February 6, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masao Moriguchi, Yohsuke Kanzaki, Yudai Takanishi, Takatsugu Kusumi
  • Publication number: 20140021038
    Abstract: An object is to provide a sputtering target capable of obtaining a film having favorable characteristics. A sputtering target (100) is configured of a plurality of target materials (10) made of IGZO, a backing plate (20) made of Cu or the like, and a bonding material (30) made of In or the like. The plurality of target materials (10) are bonded with the backing plate (20) via the bonding material 30. A groove (40) having a length (L2), a width (W3) and a depth (D1) is provided on the surface of each target material (10). This groove (40) is provided parallel to a joint (15) of the mutually adjacent target materials (10) in the vicinity of the joint (15) (position with a distance (W2) from the joint (15)). The width (W3) of the groove (40) and the distance (W2) between the joint (15) and the groove (40) are sufficiently smaller than the length (L1) of each of upper and lower sides of the target material (10).
    Type: Application
    Filed: February 23, 2012
    Publication date: January 23, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Takatsugu Kusumi, Yohsuke Kanzaki
  • Publication number: 20140009706
    Abstract: A TFT 1 is formed on a glass substrate 11, and a flattening resin film 17 covering the TFT 1 is formed. Furthermore, a moisture-proof protective film 18 covering the entire surface of the flattening resin film 17 is formed. For the protective film 18, a SiO2 film, a SiN film, a SiON film, or a stacked film thereof is used. The edge surfaces of the flattening resin film 17 are disposed on the inner side of or under a seal 4, and are formed in a tapered shape. By this, the entry of moisture into the flattening resin film 17 is prevented, preventing display degradation. This effect becomes noticeable in a display device including an oxide semiconductor TFT.
    Type: Application
    Filed: March 16, 2012
    Publication date: January 9, 2014
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masao Moriguchi, Yohsuke Kanzaki, Yudai Takanishi, Takatsugu Kusumi
  • Publication number: 20130285054
    Abstract: A semiconductor device according to the present invention includes: a gate electrode (62) of a thin film transistor (10) and an oxygen supply layer (64), the gate electrode (62) and the oxygen supply layer (64) being formed on a substrate (60); a gate insulating layer (66) formed on the gate electrode (62) and the oxygen supply layer (64); an oxide semiconductor layer (68) of the thin film transistor (10), the oxide semiconductor layer (68) being formed on the gate insulating layer (66); and a source electrode (70S) and a drain electrode (70d) of the thin film transistor (10), the source electrode (70S) and the drain electrode (70d) being formed on the gate insulating layer (66) and the oxide semiconductor layer (68).
    Type: Application
    Filed: December 6, 2011
    Publication date: October 31, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masao Moriguchi, Yohsuke Kanzaki, Yudai Takanishi, Takatsugu Kusumi, Hiroshi Matsukizono
  • Publication number: 20130175521
    Abstract: A TFT 20 includes a gate electrode 21, a gate insulating film 22, a semiconductor layer 23, a source electrode 24, a drain electrode 25, etc. The semiconductor layer 23 is comprised of a metal oxide semiconductor (IGZO), and has a source portion 23a that contacts the source electrode 24, a drain electrode 23b that contacts the drain electrode 25, and a channel portion 23c that is located between the source and drain portions 23a, 23b. A reduced region 30 is formed at least in the channel portion 23c of the semiconductor layer 23, and the reduced region 30 has a higher content of a simple substance of a metal such as In than the remaining portion of the semiconductor layer 23.
    Type: Application
    Filed: May 23, 2011
    Publication date: July 11, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masao Moriguchi, Michiko Takei, Yohsuke Kanzaki, Tsuyoshi Inoue, Tetsuo Fukaya, Yudai Takanishi, Takatsugu Kusumi, Yoshiki Nakatani, Tetsuya Okamoto, Kenji Nakanishi