Abstract: A memory system includes a ferroelectric memory, flash EEPROM, control circuit, and interface circuit. The control circuit is configured to control the ferroelectric memory and flash EEPROM. The interface circuit is configured to communicate externally. Data is programmed in the flash EEPROM by a write unit which is smaller than a block as an erase unit and larger than a page as a program unit. The ferroelectric memory stores a logical address-physical address conversion table using the write unit.

Abstract: A memory device used attach to a host system includes a nonvolatile memory including a plurality of blocks, each of the blocks being a unit for data erasure and including a plurality of pages, each of the pages including a data section which stores first data supplied from the host system, and a redundancy section which stores at least second data used to manage the first data, a detection circuit which generates a first code used to detect a first error contained in the second data, and detects the first error based on the first code, and a correction circuit which generates a second code used to detect and correct a second error contained in the first data and the second data, and detects and corrects the second error based on the second code.

Abstract: A memory management device for managing a nonvolatile semiconductor memory which comprises a plurality of blocks, and permits data to be erased in units of one block, the memory management device comprises a setting unit configured to set an address range of data to be erased in response to an erase command in a block in which the data to be erased is written, when the erase command is issued with respect to the nonvolatile semiconductor memory and a controlling unit configured to output initial-value data as data to be read in response to a data read command, when the data read command is issued with respect to the nonvolatile semiconductor memory, and then when an address range of the data to be read in response to the data read command is included in the address range set by the setting unit.

Abstract: A system for authenticating a memory card including: a memory card host device including a plural area authentication module which judges whether the memory card has plural storage areas, and an area switching module which switches a storage area subject to access a different storage area from among plural storage areas; a memory card including plural storage areas, at least one internal register which retains a value indicating the number of storage areas, and a controller which transmits the value indicating the number of the storage areas to the memory card host device; and a bus which transmits and receives data between the memory card host device and the memory card.

Abstract: A memory device used attach to a host system includes a nonvolatile memory including a plurality of blocks, each of the blocks being a unit for data erasure and including a plurality of pages, each of the pages including a data section which stores first data supplied from the host system, and a redundancy section which stores at least second data used to manage the first data, a detection circuit which generates a first code used to detect a first error contained in the second data, and detects the first error based on the first code, and a correction circuit which generates a second code used to detect and correct a second error contained in the first data and the second data, and detects and corrects the second error based on the second code.

Abstract: A memory system includes a ferroelectric memory, flash EEPROM, control circuit, and interface circuit. The control circuit is configured to control the ferroelectric memory and flash EEPROM. The interface circuit is configured to communicate externally. Data is programmed in the flash EEPROM by a write unit which is smaller than a block as an erase unit and larger than a page as a program unit. The ferroelectric memory stores a logical address-physical address conversion table using the write unit.

Abstract: A memory system includes a ferroelectric memory formed by arranging a plurality of memory cells having a ferroelectric capacitor and cell transistor, a flash EEPROM formed by arranging a plurality of memory cells having a floating gate and capable of electrically erasing and writing data, a control circuit configured to control the ferroelectric memory and flash EEPROM, and an interface circuit configured to communicate with the outside. The flash EEPROM stores data. The ferroelectric memory stores at least one of root information for storing the data, directory information, the file name of the data, the file size of the data, file allocation table information storing the storage location of the data, and the write completion time of the data.

Abstract: A system for authenticating a memory card including: a memory card host device including a plural area authentication module which judges whether the memory card has plural storage areas, and an area switching module which switches a storage area subject to access a different storage area from among plural storage areas; a memory card including plural storage areas, at least one internal register which retains a value indicating the number of storage areas, and a controller which transmits the value indicating the number of the storage areas to the memory card host device; and a bus which transmits and receives data between the memory card host device and the memory card.

Abstract: A memory management device for managing a nonvolatile semiconductor memory which comprises a plurality of blocks, and permits data to be erased in units of one block, the memory management device comprises a setting unit configured to set an address range of data to be erased in response to an erase command in a block in which the data to be erased is written, when the erase command is issued with respect to the nonvolatile semiconductor memory and a controlling unit configured to output initial-value data as data to be read in response to a data read command, when the data read command is issued with respect to the nonvolatile semiconductor memory, and then when an address range of the data to be read in response to the data read command is included in the address range set by the setting unit.

Abstract: A memory management device for managing a nonvolatile semiconductor memory which comprises a plurality of blocks, and permits data to be erased in units of one block, the memory management device comprises a setting unit configured to set an address range of data to be erased in response to an erase command in a block in which the data to be erased is written, when the erase command is issued with respect to the nonvolatile semiconductor memory and a controlling unit configured to output initial-value data as data to be read in response to a data read command, when the data read command is issued with respect to the nonvolatile semiconductor memory, and then when an address range of the data to be read in response to the data read command is included in the address range set by the setting unit.

Abstract: A memory management device for managing a nonvolatile semiconductor memory which comprises a plurality of blocks, and permits data to be erased in units of one block, the memory management device comprises a setting unit configured to set an address range of data to be erased in response to an erase command in a block in which the data to be erased is written, when the erase command is issued with respect to the nonvolatile semiconductor memory and a controlling unit configured to output initial-value data as data to be read in response to a data read command, when the data read command is issued with respect to the nonvolatile semiconductor memory, and then when an address range of the data to be read in response to the data read command is included in the address range set by the setting unit.

Abstract: A control section includes an address information detection section detecting address information from a write command including address information, an address information storage section storing address information, and a first address determination section determining whether or not the address information detected by the address information detection section matches with the address information stored in the address information storage section. The control section stores directory entry information corresponding to the address information in the second storage section when receiving matching information from the first address determination section.

Abstract: A system for authenticating a memory card including: a memory card host device including a plural area authentication module which judges whether the memory card has plural storage areas, and an area switching module which switches a storage area subject to access a different storage area from among plural storage areas; a memory card including plural storage areas, at least one internal register which retains a value indicating the number of storage areas, and a controller which transmits the value indicating the number of the storage areas to the memory card host device; and a bus which transmits and receives data between the memory card host device and the memory card.