Patents by Inventor Takayasu Ito

Takayasu Ito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110204957
    Abstract: The semiconductor integrated circuit is provided, in which an external temperature control or temperature monitoring is possible, with little influence by the noise of a system board which mounts the semiconductor integrated circuit. The semiconductor integrated circuit includes the temperature detection circuit which detects the chip temperature, and the functional module which flows a large operating current. An external terminal which supplies operating voltage, and an external terminal which supplies ground voltage are coupled to the functional module. The temperature detection circuit generates a temperature detection signal and a reference signal. The reference signal and the temperature detection signal are led out to the exterior of the semiconductor integrated circuit via a first external output terminal and a second external output terminal, respectively, and are supplied to an external temperature control/monitoring circuit which has a circuitry type of a differential amplifier circuit.
    Type: Application
    Filed: May 6, 2011
    Publication date: August 25, 2011
    Inventors: TADASHI KAMEYAMA, Takayasu Ito, Seiichi Saito, Koji Sato
  • Patent number: 7948298
    Abstract: The semiconductor integrated circuit is provided, in which an external temperature control or temperature monitoring is possible, with little influence by the noise of a system board which mounts the semiconductor integrated circuit. The semiconductor integrated circuit includes the temperature detection circuit which detects the chip temperature, and the functional module which flows a large operating current. An external terminal which supplies operating voltage, and an external terminal which supplies ground voltage are coupled to the functional module. The temperature detection circuit generates a temperature detection signal and a reference signal. The reference signal and the temperature detection signal are led out to the exterior of the semiconductor integrated circuit via a first external output terminal and a second external output terminal, respectively, and are supplied to an external temperature control/monitoring circuit which has a circuitry type of a differential amplifier circuit.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: May 24, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tadashi Kameyama, Takayasu Ito, Seiichi Saito, Koji Sato
  • Publication number: 20110090605
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Application
    Filed: December 23, 2010
    Publication date: April 21, 2011
    Inventors: Takayasu ITO, Mitsuru Hiraki, Koichi Ashiga
  • Publication number: 20110090001
    Abstract: A semiconductor integrated circuit device which substantially reduces drop in a supply voltage generated by a regulator and ensures stable supply of a supply voltage with high efficiency and high accuracy. In the device, a memory power supply includes a plurality of transistors and an error amplifier. In the transistors, source pads and drain pads are alternately arranged in a row along one edge of a semiconductor chip in a peripheral area of the chip. Transistor gates are formed in parallel with the alternately arranged source pads and drain pads (so that the longitudinal direction of the gates is parallel to the direction of the arrangement of the source pads and drain pads). Consequently, the length of wirings coupled to drains and sources is shortened and the sheet resistance is decreased.
    Type: Application
    Filed: December 28, 2010
    Publication date: April 21, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Naoya ARISAKA, Takayasu ITO
  • Patent number: 7881026
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: February 1, 2011
    Assignees: Renesas Electronics Corporation, Hitachi Device Engineering Co., Ltd.
    Inventors: Takayasu Ito, Mitsuru Hiraki, Koichi Ashiga
  • Patent number: 7872520
    Abstract: A semiconductor integrated circuit device which substantially reduces drop in a supply voltage generated by a regulator and ensures stable supply of a supply voltage with high efficiency and high accuracy. In the device, a memory power supply includes a plurality of transistors and an error amplifier. In the transistors, source pads and drain pads are alternately arranged in a row along one edge of a semiconductor chip in a peripheral area of the chip. Transistor gates are formed in parallel with the alternately arranged source pads and drain pads (so that the longitudinal direction of the gates is parallel to the direction of the arrangement of the source pads and drain pads). Consequently, the length of wirings coupled to drains and sources is shortened and the sheet resistance is decreased.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: January 18, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Naoya Arisaka, Takayasu Ito
  • Publication number: 20100327841
    Abstract: The present invention provides a technique for reducing current consumption in a reference voltage forming circuit without a significant increase in area while suppressing considerable degradative difference in reference voltage accuracy between a normal operation mode and a standby mode. In the standby mode, by using a clock signal fed from an oscillator circuit, the frequency-division control circuit produces an enable signal VREFON for determining ON/OFF states of the reference voltage generator circuit, the reference voltage forming circuit, and the capacitance charging regulator, and also produces a sampling/holding signal CHOLDSW for performing control so that a holding capacitor CH in a holding capacitance circuit is charged during an ON period of the reference voltage generator circuit, the reference voltage forming circuit, and the capacitance charging regulator, and so that any paths other than a leak current path are made unavailable to the holding capacitor CH during an OFF period thereof.
    Type: Application
    Filed: June 8, 2010
    Publication date: December 30, 2010
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Takayasu ITO, Mitsuru HIRAKI, Masashi HORIGUCHI
  • Publication number: 20100301924
    Abstract: The semiconductor integrated circuit is provided, in which an external temperature control or temperature monitoring is possible, with little influence by the noise of a system board which mounts the semiconductor integrated circuit. The semiconductor integrated circuit includes the temperature detection circuit which detects the chip temperature, and the functional module which flows a large operating current. An external terminal which supplies operating voltage, and an external terminal which supplies ground voltage are coupled to the functional module. The temperature detection circuit generates a temperature detection signal and a reference signal. The reference signal and the temperature detection signal are led out to the exterior of the semiconductor integrated circuit via a first external output terminal and a second external output terminal, respectively, and are supplied to an external temperature control/monitoring circuit which has a circuitry type of a differential amplifier circuit.
    Type: Application
    Filed: August 5, 2010
    Publication date: December 2, 2010
    Inventors: TADASHI KAMEYAMA, Takayasu Ito, Seiichi Saito, Koji Sato
  • Patent number: 7782119
    Abstract: The semiconductor integrated circuit is provided, in which an external temperature control or temperature monitoring is possible, with little influence by the noise of a system board which mounts the semiconductor integrated circuit. The semiconductor integrated circuit includes the temperature detection circuit which detects the chip temperature, and the functional module which flows a large operating current. An external terminal which supplies operating voltage, and an external terminal which supplies ground voltage are coupled to the functional module. The temperature detection circuit generates a temperature detection signal and a reference signal. The reference signal and the temperature detection signal are led out to the exterior of the semiconductor integrated circuit via a first external output terminal and a second external output terminal, respectively, and are supplied to an external temperature control/monitoring circuit which has a circuitry type of a differential amplifier circuit.
    Type: Grant
    Filed: April 13, 2009
    Date of Patent: August 24, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Tadashi Kameyama, Takayasu Ito, Seiichi Saito, Koji Sato
  • Publication number: 20100045368
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Application
    Filed: October 27, 2009
    Publication date: February 25, 2010
    Inventors: Takayasu Ito, Mitsuru Hiraki, Koichi Ashiga
  • Publication number: 20100019835
    Abstract: A semiconductor integrated circuit device which substantially reduces drop in a supply voltage generated by a regulator and ensures stable supply of a supply voltage with high efficiency and high accuracy. In the device, a memory power supply includes a plurality of transistors and an error amplifier. In the transistors, source pads and drain pads are alternately arranged in a row along one edge of a semiconductor chip in a peripheral area of the chip. Transistor gates are formed in parallel with the alternately arranged source pads and drain pads (so that the longitudinal direction of the gates is parallel to the direction of the arrangement of the source pads and drain pads). Consequently, the length of wirings coupled to drains and sources is shortened and the sheet resistance is decreased.
    Type: Application
    Filed: June 1, 2009
    Publication date: January 28, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Naoya ARISAKA, Takayasu ITO
  • Patent number: 7652863
    Abstract: In order to set with a high precision the value of rush current flowing in the power switch circuit at the time of turning “on” the power, the internal circuit Int_Cir of the LSI is supplied with the internal source voltage Vint from the output transistor MP1 of the regulator VReg of the power switch circuit PSWC. The power switch circuit PSWC includes a control circuit CNTRLR and a start-up circuit STC. During the initial period Tint following the turning “on” of the power supply, the start-up circuit STC controls the output transistor MP1 and reduces the primary rush current so that the output current Isup of the output transistor MP1 may represent an approximately constant increment as the time passes. The difference ?V between the internal current voltage due to the charge of load capacitance C with the output current Isup controlled by the start-up circuit STC and the current voltage Vint from the regulator VReg is set within the predetermined limit to reduce the secondary rush current.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: January 26, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Takayasu Ito, Mitsuru Hiraki, Satoshi Baba, Kenichi Fukui
  • Patent number: 7630178
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: December 8, 2009
    Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd.
    Inventors: Takayasu Ito, Mitsuru Hiraki, Koichi Ashiga
  • Publication number: 20090295458
    Abstract: The semiconductor integrated circuit is provided, in which an external temperature control or temperature monitoring is possible, with little influence by the noise of a system board which mounts the semiconductor integrated circuit. The semiconductor integrated circuit includes the temperature detection circuit which detects the chip temperature, and the functional module which flows a large operating current. An external terminal which supplies operating voltage, and an external terminal which supplies ground voltage are coupled to the functional module. The temperature detection circuit generates a temperature detection signal and a reference signal. The reference signal and the temperature detection signal are led out to the exterior of the semiconductor integrated circuit via a first external output terminal and a second external output terminal, respectively, and are supplied to an external temperature control/monitoring circuit which has a circuitry type of a differential amplifier circuit.
    Type: Application
    Filed: April 13, 2009
    Publication date: December 3, 2009
    Inventors: Tadashi KAMEYAMA, Takayasu ITO, Seiichi SAITO, Koji SATO
  • Publication number: 20090039846
    Abstract: In order to set with a high precision the value of rush current flowing in the power switch circuit at the time of turning “on” the power, the internal circuit Int_Cir of the LSI is supplied with the internal source voltage Vint from the output transistor MP1 of the regulator VReg of the power switch circuit PSWC. The power switch circuit PSWC includes a control circuit CNTRLR and a start-up circuit STC. During the initial period Tint following the turning “on” of the power supply, the start-up circuit STC controls the output transistor MP1 and reduces the primary rush current so that the output current Isup of the output transistor MP1 may represent an approximately constant increment as the time passes. The difference ?V between the internal current voltage due to the charge of load capacitance C with the output current Isup controlled by the start-up circuit STC and the current voltage Vint from the regulator VReg is set within the predetermined limit to reduce the secondary rush current.
    Type: Application
    Filed: October 15, 2008
    Publication date: February 12, 2009
    Inventors: Takayasu Ito, Mitsuru Hiraki, Satoshi Baba, Kenichi Fukui
  • Publication number: 20080285185
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Application
    Filed: July 25, 2008
    Publication date: November 20, 2008
    Inventors: TAKAYASU ITO, Mitsuru Hiraki, Koichi Ashiga
  • Patent number: 7450361
    Abstract: In order to set with a high precision the value of rush current flowing in the power switch circuit at the time of turning “on” the power, the internal circuit Int_Cir of the LSI is supplied with the internal source voltage Vint from the output transistor MP1 of the regulator VReg of the power switch circuit PSWC. The power switch circuit PSWC includes a control circuit CNTRLR and a start-up circuit STC. During the initial period Tint following the turning “on” of the power supply, the start-up circuit STC controls the output transistor MP1 and reduces the primary rush current so that the output current Isup of the output transistor MP1 may represent an approximately constant increment as the time passes. The difference ?V between the internal current voltage due to the charge of load capacitance C with the output current Isup controlled by the start-up circuit STC and the current voltage Vint from the regulator VReg is set within the predetermined limit to reduce the secondary rush current.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: November 11, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Takayasu Ito, Mitsuru Hiraki, Satoshi Baba, Kenichi Fukui
  • Publication number: 20080228414
    Abstract: The present invention provides a semiconductor device capable of realizing power saving and improvement in reliability or reduction in area. A semiconductor device includes: a power switch connecting an internal power supply in which power is not shut down and an internal power supply in which power is shut down; and an internal voltage determining circuit for determining voltage of the internal power supply in which power is shut down. Voltage of the internal power supply in which power is shut down is generated from voltage of an external power supply by using a regulator circuit. When the power of the internal power supply is interrupted, the power switch is turned off, the regulator circuit is turned off, and an output of the regulator circuit is shorted to a ground potential.
    Type: Application
    Filed: May 18, 2008
    Publication date: September 18, 2008
    Inventors: Takayasu ITO, Mitsuru Hiraki, Masashi Horiguchi, Toyohiro Shimogawa
  • Patent number: 7417838
    Abstract: An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: August 26, 2008
    Assignees: Renesas Technology Corp., Hitachi Device Engineering Co., Ltd.
    Inventors: Takayasu Ito, Mitsuru Hiraki, Koichi Ashiga
  • Patent number: RE41270
    Abstract: For an internal circuit having a first operation mode consuming a first operational current and a second operation mode consuming a second operational current, which is smaller than the first operational current, a first power source regulator for stepping down a predefined output power supply voltage from an input power supply voltage and having a current supply ability corresponding to the first operational current of the internal circuit and a second power source gulator having a current supply ability corresponding to the second operational current are combined in order to, under the control of a power supply control unit, operate the first step-down type regulator in response to a first control signal instructing the first operation mode in the internal circuit and to operate the second step-down type regulator in response to a second control signal instructing the second operation mode.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: April 27, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Mitsuru Hiraki, Takayasu Ito