Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.

Abstract: Provided are an active ingredient-containing particle with improved shape retainability. The particle includes a first fraction containing an active ingredient, a second fraction containing a surfactant, and at least one water-soluble polymer selected from the group consisting of a polysaccharide and a polymer having 2-methacryloyloxyethyl phosphorylcholine as a constituent unit.

Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.

Abstract: According to one embodiment, in a case where a first command is received from a host, a storage device starts a first process. The storage device transmits a first response to the host in a case where a first condition is satisfied and transmits a second response and an interrupt signal to the host in a case where the first process is completed. The host, in a case where the first response is received, stops the polling and receives the second response based on reception of the interrupt signal.

Abstract: Provided is a core-shell structure having an excellent immediate effect in transdermal absorption of an active ingredient. A core-shell structure comprising a core portion containing an active ingredient, and a shell portion containing a surfactant having an HLB value of 4 to 14, the core portion being solid, and the surfactant containing a saturated hydrocarbon group having 7 to 15 carbon atoms or an unsaturated hydrocarbon group having 7 to 17 carbon atoms.

Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.

Abstract: An object is to provide a formulation that includes a particle containing an active ingredient and a surfactant, and a base, and is more excellent in storage stability. For solution, a formulation including a particle containing an active ingredient and a surfactant, and a base, in which the surfactant is contained in a ratio of 5 to 100 parts by weight based on 1 part by weight of the active ingredient, is provided.

Abstract: Provided are an active ingredient-containing particle with improved shape retainability. The particle includes a first fraction containing an active ingredient, a second fraction containing a surfactant, and at least one water-soluble polymer selected from the group consisting of a polysaccharide and a polymer having 2-methacryloyloxyethyl phosphorylcholine as a constituent unit.

Abstract: An object of the present invention is to prevent a particle including a first fraction containing an active ingredient and a second fraction containing a surfactant from bleeding out from the base phase of an external preparation. The external preparation comprises a particle including a first fraction containing an active ingredient and a second fraction containing a surfactant, and a base phase containing a gelatinous liquid component.

Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.

Abstract: The present invention provides a core-shell structure having high skin permeability. The core-shell structure includes a core portion containing a hydrophilic drug having a molecular weight of 400 or more; and a shell portion containing a surfactant, and the core portion is a solid, the hydrophilic drug has a water-octanol partition coefficient of ?3 or more and 6 or less, the surfactant has an alkyl group or an alkenyl group having 10 to 20 carbon atoms, and a mass ratio between the hydrophilic drug and the surfactant (hydrophilic drug:surfactant) is 1:5 to 1:20.

Abstract: According to one embodiment, in a case where a first command is received from a host, a storage device starts a first process. The storage device transmits a first response to the host in a case where a first condition is satisfied and transmits a second response and an interrupt signal to the host in a case where the first process is completed. The host, in a case where the first response is received, stops the polling and receives the second response based on reception of the interrupt signal.

Abstract: According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.

Abstract: An information processing system includes a first core, a second core having a processing speed that is slower than the first core, a first memory, a second memory having a slower response time than the first memory, and a management processor. The management processor is configured to determine a core for executing a task, cause program data for executing the task to be copied to the first memory and then cause the first core to execute the task using the program data in the first memory, when the first core is determined as the core for executing the task, and cause the program data for executing the task to be copied to the second memory and then cause the second core to execute the task using the program data in the second memory, when the second core is determined as the core for executing the task.

Abstract: A particle comprising a first fraction containing an active ingredient and a second fraction containing a surfactant, and having a number average particle diameter of from 1 to 100 nm.

Abstract: A semiconductor memory device includes: a first memory unit including first to fourth memory cells; a second memory unit including fifth to eighth memory cells; a first word line coupled to gates of the first and fifth memory cells; a second word line coupled to gates of the second and sixth memory cells; a third word line coupled to gates of the third and seventh memory cells; and a fourth word line coupled to gates of the fourth and eighth memory cells. In a write operation, writes to the fourth memory cell, the first memory cell, the eighth memory cell, and the fifth memory cell are executed in order.

Abstract: According to one embodiment, a semiconductor memory device includes: a first memory unit including first to fourth memory cells; a second memory unit including fifth to eighth memory cells; a first word line coupled to gates of the first and fifth memory cells; a second word line coupled to gates of the second and sixth memory cells; a third word line coupled to gates of the third and seventh memory cells; and a fourth word line coupled to gates of the fourth and eighth memory cells. In a write operation, writes to the fourth memory cell, the first memory cell, the eighth memory cell, and the fifth memory cell are executed in order.

Abstract: An object is to provide a formulation that includes a particle containing an active ingredient and a surfactant, and a base, and is more excellent in storage stability. For solution, a formulation including a particle containing an active ingredient and a surfactant, and a base, in which the surfactant is contained in a ratio of 5 to 100 parts by weight based on 1 part by weight of the active ingredient, is provided.

Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.

Abstract: A semiconductor memory device includes: a first string unit including first and second memory cell transistors; a second string unit including third and fourth memory cell transistors; a first word line coupled to gates of the first and third memory cell transistors; and a second word line coupled to gates of the second and fourth memory cell transistors. When the first string unit is selected and the first word line is selected, a first voltage is applied. The first voltage is larger than an initial value of the voltage in the step-up operation.