Abstract: A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.

Abstract: A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.

Abstract: A semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip is configured to achieve higher speed operation at a lower voltage. The semiconductor device includes a nonvolatile memory unit comprising a plurality of rewritable nonvolatile memory cells and a variable logic unit whose logical functions are determined, according to logic constitution definition data to be loaded into storage cells thereof. A nonvolatile memory cell essentially has a split gate structure composed of a selecting MOS transistor and a memory MOS transistor and constructed such that the dielectric withstand voltage of the gate of the selecting MOS transistor is lower than that of the memory MOS transistor or the gate insulation layer of the selecting MOS transistor is thinner than that of a high-voltage-tolerant MOS transistor. Because the selecting MOS transistor has a high Gm, a sufficiently great current for reading can be obtained.

Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.

Abstract: It is an object of the present invention to allow a voltage generating section which produces a high voltage to efficiently produce a high voltage, and to reduce a layout area of a semiconductor chip. An intermediate voltage charge pump circuit is provided in a voltage producing section of a flash memory. The intermediate voltage charge pump circuit comprises switching elements, a first charge pump circuit comprising capacitors, a second charge pump circuit comprising switching elements, capacitors and an equalizer comprising switching elements. These elements are driven by driving signals. A period during which all of one contacts of parasitic capacities Capacitor are brought into floating state temporarily is formed. After corresponding parasitic capacities are short-circuited by the switching elements, nodes thereof are electrically charged or discharged, and a high voltage is produced while reusing electric charge while using electric charge discharged to a reference potential by next cycle.

Abstract: The present invention discloses a nonvolatile semiconductor memory device including a memory cell array composed of a plurality of memory cells, each of which is formed with a gate insulating film, a floating gate electrode, an insulating film between electrodes, and a control electrode formed respectively in a first conductor type semiconductor area, as well as a second conductor type source area and a second conductor type drain area formed respectively in the firs conductor type semiconductor area, and programming and erasing data by controlling the amount of electrons in the floating gate electrode, wherein the nonvolatile semiconductor memory device further includes at least; means for applying a predetermined first operation voltage to the memory cell thereby to inject or eject electrons in or from the floating gate electrode; means for applying a second operation voltage to the memory cell after the application of the first operation voltage to give an electric field with a polarity opposite to that of

Abstract: A structure for attaching a pellicle to a photomask, the pellicle comprising a pellicle frame and a pellicle sheet attached to an opening portion formed in the pellicle frame, wherein at least a portion of the pellicle frame surface in contact with the photo-mask has a direct contact with the photo-mask without interposing an adhesive.

Abstract: A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.

Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.

Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Abstract: A reference voltage generator to operate under the supply voltage of 1V or less is provided. In order to output a reference voltage, the change as caused by the ambient temperature of the forward bias voltage of any one of the plural Schottky diodes is compensated with the difference in the forward bias voltage between said plural Schottky diodes. The semiconductor region corresponding to the Schottky contact interface is formed in the same process as for an N well region corresponding to the channel region of the PMOS transistor or for a P well region corresponding to the channel region of the NMOS transistor and the metallic region thereof corresponding to the Schottky contact interface is formed in the same process as for the silicide region comprising the contact region of the MOS transistor.

Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Abstract: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.

Abstract: It is an object of the present invention to provide a security system and security apparatus with excellent user-friendliness. A receiver 5 acquires the phone number of a cellular phone carried by a visitor, the transfer function unit 204 checks the phone number thus acquired against the phone number of an anticipated visitor to identify the visitor, and transfers the information to a personal digital assistant (PDA) unit to be redirected if the transfer is judged to be necessary.

Abstract: A control of a flash memory includes control for supplying a pulse-shaped voltage to each of non-volatile memory cells until a threshold voltage of the non-volatile memory cell having a first threshold voltage is changed to a second threshold voltage. The control involves a first write mode (coarse write) in which the amount of change in threshold voltage of each non-volatile memory cell, which is varied each time the pulse-shaped voltage is applied, is relatively rendered high, and a second write mode (high-accuracy write) in which the amount of change in threshold voltage thereof is relatively rendered low. As compared with the high-accuracy mode, the number of pulses required to change the threshold voltage of each memory cell is smaller than that in the coarse write mode. Therefore, the number of verify operations at the time that the coarse write mode is used, is small and hence the entire write operation can be speeded up.

Abstract: To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages arc applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.

Abstract: A data processing system used for a net-order sale or the like includes a host apparatus connectable to a terminal apparatus via a network. The host apparatus includes a database in which cryptographic keys are registered in being caused to correspond to user IDs. The cryptographic keys are caused to be related in a one-to-one manner to appliance manufacture numbers of domestic electrical apparatuses onto which terminal apparatuses are integrated. The host apparatus retrieves, from the database, a cryptographic key corresponding to a user ID that accompanies a transaction request from the terminal apparatus. Using the retrieved cryptographic key, the host apparatus performs encryption/decryption processings of information data transmitted/received between the terminal apparatus and the host apparatus. Information having a one-to-one correspondence relationship with the appliance manufacture number of the domestic electrical apparatus is utilized as the whole of the cryptographic key.

Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.

Abstract: A semiconductor device having a functional circuit block with predictive power controller is provided so as to construct a system LSI manufactured in the practicable number of design steps, which is extensible and in which power is reduced. The functional circuit block includes a prediction circuit and a predictive power shutdown circuit having a power status control circuit. The prediction circuit controls a power status of the functional circuit block by using the power status control circuit, based on input information thereto. When no information is inputted for a predetermined a period of time, the power status control circuit shifts to a power status of the functional circuit block to a low-power status.

Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.