Abstract: A hybrid compressor includes a first compression mechanism, which is driven by a first drive source, and a second compression mechanism, which is driven by a second drive source, and a second radial axis of a second housing of the second compression mechanism is offset relative to a first radial axis of a first housing of the first compression mechanism, or a second diameter of the second housing of the second compression mechanism is less than a first diameter of the first housing of the first compression mechanism, or both. When a significant external force is applied to the front end of a vehicle containing the compressor, most of the external force may be absorbed by the first compression mechanism portion of the compressor, thereby reducing or avoiding damage to the second compression mechanism. In particular, when the second drive source is an incorporated electric motor, damage to the electric motor may be reduced or avoided.

Abstract: A semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip is configured to achieve higher speed operation at a lower voltage. The semiconductor device includes a nonvolatile memory unit comprising a plurality of rewritable nonvolatile memory cells and a variable logic unit whose logical functions are determined, according to logic constitution definition data to be loaded into storage cells thereof. A nonvolatile memory cell essentially has a split gate structure composed of a selecting MOS transistor and a memory MOS transistor and constructed such that the dielectric withstand voltage of the gate of the selecting MOS transistor is lower than that of the memory MOS transistor or the gate insulation layer of the selecting MOS transistor is thinner than that of a high-voltage-tolerant MOS transistor. Because the selecting MOS transistor has a high Gm, a sufficiently great current for reading can be obtained.

Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.

Abstract: A method for driving a hybrid compressor of an air conditioning system of a vehicle is provided. The vehicle includes a first drive source, and the air conditioning system includes an evaporator. Moreover, the hybrid compressor includes a second drive source, and the hybrid compressor is driven by the first drive source via an electromagnetic clutch or the second drive source, or combination thereof. The method includes the steps of engaging the electromagnetic clutch, detecting a temperature of air dispensed from the evaporator, and disengaging the electromagnetic clutch when the temperature of the air is equal to a predetermined temperature. The method also includes the step of activating the second drive source. Specifically the step of disengaging the electromagnetic clutch when the temperature of the air is equal to the predetermined temperature and the step of activating the second drive source is performed simultaneously or substantially simultaneously.

Abstract: To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.

Abstract: A structure for attaching a pellicle to a photomask, the pellicle comprising a pellicle frame and a pellicle sheet attached to an opening portion formed in the pellicle frame, wherein at least a portion of the pellicle frame surface in contact with the photo-mask has a direct contact with the photo-mask without interposing an adhesive.

Abstract: A semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip is configured to achieve higher speed operation at a lower voltage. The semiconductor device includes a nonvolatile memory unit comprising a plurality of rewritable nonvolatile memory cells and a variable logic unit whose logical functions are determined, according to logic constitution definition data to be loaded into storage cells thereof. A nonvolatile memory cell essentially has a split gate structure composed of a selecting MOS transistor and a memory MOS transistor and constructed such that the dielectric withstand voltage of the gate of the selecting MOS transistor is lower than that of the memory MOS transistor or the gate insulation layer of the selecting MOS transistor is thinner than that of a high-voltage-tolerant MOS transistor. Because the selecting MOS transistor has a high Gm, a sufficiently great current for reading can be obtained.

Abstract: It is an object of the present invention to allow a voltage generating section which produces a high voltage to efficiently produce a high voltage, and to reduce a layout area of a semiconductor chip. An intermediate voltage charge pump circuit is provided in a voltage producing section of a flash memory. The intermediate voltage charge pump circuit comprises switching elements, a first charge pump circuit comprising capacitors, a second charge pump circuit comprising switching elements, capacitors and an equalizer comprising switching elements. These elements are driven by driving signals. A period during which all of one contacts of parasitic capacities Capacitor are brought into floating state temporarily is formed. After corresponding parasitic capacities are short-circuited by the switching elements, nodes thereof are electrically charged or discharged, and a high voltage is produced while reusing electric charge while using electric charge discharged to a reference potential by next cycle.

Abstract: Thresholds of MISFETS of a Full Depletion-type SOI substrate cannot be controlled by changing impurity density as with bulk silicon MISFETs. Therefore, it is difficult to set a suitable threshold for each circuit. According to the semiconductor device of the present invention, gate electrodes of P-channel type MISFETs composing a memory cell are made of N-type polysilicon, gate electrodes of N-channel type MISFETs are made of P-type polysilicon and gate electrodes of P-channel type and N-channel type MISFETs of peripheral circuits and a logic circuit are made of P-type silicon germanium. A suitable threshold can be achieved for each circuit using a SOI substrate, thereby making it possible to fully leverage the characteristics of the SOI substrate.

Abstract: A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.

Abstract: To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.

Abstract: The present invention discloses a nonvolatile semiconductor memory device including a memory cell array composed of a plurality of memory cells, each of which is formed with a gate insulating film, a floating gate electrode, an insulating film between electrodes, and a control electrode formed respectively in a first conductor type semiconductor area, as well as a second conductor type source area and a second conductor type drain area formed respectively in the first conductor type semiconductor area, and programming and erasing data by controlling the amount of electrons in the floating gate electrode, wherein the nonvolatile semiconductor memory device further includes at least; means for applying a predetermined first operation voltage to the memory cell thereby to inject or eject electrons in or from the floating gate electrode; means for applying a second operation voltage to the memory cell after the application of the first operation voltage to give an electric field with a polarity opposite to that o

Abstract: A semiconductor non-volatile storage device of the present invention which lets a memory cell directly drive up to a local bit line, wherein the output of the local bit line is received by a gate electrode of a separately-provided signal amplifying transistor, and the signal amplifying transistor is used t drive a global bit line having a large load capacity. Since an amplifying transistor having a drive power higher than a memory cell drives the parasitic capacity of a global bit line, information stored in a memory cell can be read out at high speed. Therefore, the storage device is used for storing program codes for controlling microcomputers or the like to thereby enhance a system performance.

Abstract: In a nonvolatile semiconductor memory in which multiple-value information is stored in one memory cell by setting a plurality of threshold values, data is successively read from word lines while continuously changing the word-line read level from a lowest level to a highest level, and the next bit line is selectively precharged in accordance with the data stored in latch means for storing read data.

Abstract: According to one aspect of the present invention, there is provided a semiconductor device comprising a plurality of memory cells, and an error-correction circuit, wherein write operation is performed by a late-write method, and ECC processing is executed in parallel with writing, and thereby cycle time is shortened. Moreover, it is better that when a memory cell is power supplied through a well tap, the same address is not assigned while the memory cell is power supplied through the well tap.

Abstract: A nonvolatile memory device of the present invention performs programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.

Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.

Abstract: A DRAM adopting a single-intersection memory cell array having randomly accessible data registers accessed whenever the chip is accessed externally. When data items recorded in the data registers are simultaneously written in the memory cell array, the data items are encoded. When data items are read from the memory cell array into the data registers, the data items are decoded. The margin is enhanced because array noise derived from reading is reduced. In addition, the access time of the DRAM is also reduced.

Abstract: A method for driving a hybrid compressor of an air conditioning system of a vehicle is provided. The vehicle includes a first drive source, and the air conditioning system includes an evaporator. Moreover, the hybrid compressor includes a second drive source, and the hybrid compressor is driven by the first drive source via an electromagnetic clutch or the second drive source, or combination thereof. The method includes the steps of engaging the electromagnetic clutch, detecting a temperature of air dispensed from the evaporator, and disengaging the electromagnetic clutch when the temperature of the air is equal to a predetermined temperature. The method also includes the step of activating the second drive source. Specifically the step of disengaging the electromagnetic clutch when the temperature of the air is equal to the predetermined temperature and the step of activating the second drive source is performed simultaneously or substantially simultaneously.

Abstract: A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The substrate voltages of the transistors are set so that the threshold voltage would be varied based on the operation mode. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.