Abstract: A tray for film formation by a CVD method includes a tray main body (2) and a supporting member (3) mounted on the tray main body (2) for supporting a silicon wafer (5). The supporting member (3) has a holding portion (3c), on which the silicon wafer (5) is directly placed. The holding portion (3c) has its lower surface (3d) apart from a surface (2a) of the tray main body that is opposed to and apart from the supported silicon wafer (5), whereby the thickness distribution of an oxide film formed on the silicon wafer can be made uniform. The tray has a structure for reducing a contact area between the supporting member (3) and the tray main body (2), with the holding portion (3c) having a tilted surface with its inner circumferential side closer to the tray main body surface (2a) that is opposed to the silicon wafer.

Abstract: A tray for film formation by a CVD method includes a tray main body (2) and a supporting member (3) mounted on the tray main body (2) for supporting a silicon wafer (5). The supporting member (3) has a holding portion (3c), on which the silicon wafer (5) is directly placed. The holding portion (3c) has its lower surface (3d) apart from a surface (2a) of the tray main body that is opposed to and apart from the supported silicon wafer (5), whereby the thickness distribution of an oxide film formed on the silicon wafer can be made uniform. The tray has a structure for reducing a contact area between the supporting member (3) and the tray main body (2), with the holding portion (3c) having a tilted surface with its inner circumferential side closer to the tray main body surface (2a) that is opposed to the silicon wafer.

Abstract: Provided is an epitaxial silicon wafer in which the warping is reduced by rendering a cross-sectional form of a silicon wafer for epitaxial growth into an adequate form as compared with the conventional one. An epitaxial silicon wafer comprising a silicon wafer for epitaxial growth and an epitaxial layer is characterized in that the epitaxial layer is formed on a silicon wafer for epitaxial growth having a cross-sectional form satisfying a relation of a given expression.

Abstract: This method of manufacturing a silicon wafer has a step of preparing a wafer, in which a surface of the silicon wafer is surface-treated, a step of setting stress, in which the stress S (MPa) subjected on the wafer is set, a step of inspecting, in which a defect on a surface of the wafer is inspected, and a step of determining, in which the wafer is evaluated if the wafer satisfies a criterion. In this method, it is possible to manufacture a wafer with cracking resistance even if it is subjected to a millisecond annealing by the FLA annealing treatment.

Abstract: Provided are an epitaxial silicon wafer in which the warping is reduced by rendering a cross-sectional form of a silicon wafer for epitaxial growth into an adequate form as compared with the conventional one, and a production method thereof. An epitaxial silicon wafer comprising a silicon wafer for epitaxial growth and an epitaxial layer is characterized in that the epitaxial layer is formed on a silicon wafer for epitaxial growth having a cross-sectional form satisfying a relation of a given expression.

Abstract: Provided is a method applicable to the production of silicon wafers having crystal orientation <100> or <110> and consisting in specifying wafer-supporting positions on the occasion of heat treatment in a vertical heat treatment furnace as well as a heat treatment jig for use in carrying out that method. It becomes possible to suppress the shear stress which contributes to the extension of the slip generated at each wafer-supporting element contact point as an initiation, suppress slip growth and thus markedly improve the yield of heat-treated silicon wafers. The heat-treated wafer obtained by using the supporting method and the heat treatment jig has few slip, in particular has no long and large slip, and is high in quality.

Abstract: Provided is a method applicable to the production of silicon wafers having crystal orientation <100> or <110> and consisting in specifying wafer-supporting positions on the occasion of heat treatment in a vertical heat treatment furnace as well as a heat treatment jig for use in carrying out that method. It becomes possible to suppress the shear stress which contributes to the extension of the slip generated at each wafer-supporting element contact point as an initiation, suppress slip growth and thus markedly improve the yield of heat-treated silicon wafers. The heat-treated wafer obtained by using the supporting method and the heat treatment jig has few slip, in particular has no long and large slip, and is high in quality.

Abstract: Provided are an epitaxial silicon wafer in which the warping is reduced by rendering a cross-sectional form of a silicon wafer for epitaxial growth into an adequate form as compared with the conventional one, and a production method thereof. An epitaxial silicon wafer comprising a silicon wafer for epitaxial growth and an epitaxial layer is characterized in that the epitaxial layer is formed on a silicon wafer for epitaxial growth having a cross-sectional form satisfying a relation of a given expression.

Abstract: The present invention is directed to provide a method for holding a silicon wafer, which can reduce contact scratches in contact with support members when holding a back surface of the silicon wafer, as well as prevent the wafer from bending when holding the back surface of the silicon wafer. The back surface of a silicon wafer of 300 millimeters or more in diameter and 700 micrometers to 1000 micrometers in thickness is held in contact with a support member or a suction member, specifically held within a region where a radius of the silicon wafer×0.50 to 0.80 from a center thereof. The silicon wafer is held in a state where the maximum amount of displacement within a wafer plane is 300 micrometers or less. The silicon wafer back surface is held in contact within the holding region in all the processes of holding the back surface of the silicon wafer in contact with the support member or the suction member.

Abstract: A production method of a silicon single crystal wafer capable of effectively bringing out a gettering effect also in a thin film device is provided: wherein a thermal treatment with rapid heating up and down is performed for 10 seconds or shorter on a silicon single crystal wafer obtained by processing a single crystal grown by the Czochralski method and having an initial interstitial oxygen density is 1.4×1018 atoms/cc (ASTM F-121, 1979).

Abstract: A high resistivity p type silicon wafer with a resistivity of 100 ?cm or more, in the vicinity of the surface being formed denuded zone, wherein when a heat treatment in the device fabrication process is performed, a p/n type conversion layer due to thermal donor generation is located at a depth to be brought into contact with neither any device active region nor depletion layer region formed in contact therewith or at a depth more than 8 ?m from the surface, and a method for fabricating the same. The high resistivity silicon wafer can cause the influence of thermal donors to disappear without reducing the soluble oxygen concentration in the wafer, whereby even if various heat treatments are performed in the device fabrication process, devices such as CMOS that offer superior characteristics can be fabricated. The wafer has wide application as a substrate for a high-frequency integrated circuit device.

Abstract: When an instruction by a person in charge is required during an analysis operation, a transmitted e-mail processing unit creates an e-mail that includes, as a message or an attached file, information concerning data to be currently analyzed and an analysis condition, and transmits the e-mail to the e-mail address of the person in charge. The person in charge, at a remote area, employs a locally available PC to read the e-mail, and transmits, to an analysis apparatus, a response e-mail that includes an instruction command. The e-mail is read through a communication controller, and a received case name confirmation unit and a sender verification unit examine the received e-mail to determine whether it is a control e-mail issued by an authorized sender. Thereafter, a command extraction unit extracts a control command from the e-mail. Upon receiving this command, an analysis controller controls the individual sections of an analysis unit.

Abstract: A high resistivity p type silicon wafer with a resistivity of 100 ?cm or more, in the vicinity of the surface being formed denuded zone, wherein when a heat treatment in the device fabrication process is performed, a p/n type conversion layer due to thermal donor generation is located at a depth to be brought into contact with neither any device active region nor depletion layer region formed in contact therewith or at a depth more than 8 ?m from the surface, and a method for fabricating the same. The high resistivity silicon wafer can cause the influence of thermal donors to disappear without reducing the soluble oxygen concentration in the wafer, whereby even if various heat treatments are performed in the device fabrication process, devices such as CMOS that offer superior characteristics can be fabricated. The wafer has wide application as a substrate for a high-frequency integrated circuit device.

Abstract: When an instruction by a person in charge is required during an analysis operation, a transmitted e-mail processing unit creates an e-mail that includes, as a message or an attached file, information concerning data to be currently analyzed and an analysis condition, and transmits the e-mail to the e-mail address of the person in charge. The person in charge, at a remote area, employs a locally available PC to read the e-mail, and transmits, to an analysis apparatus, a response e-mail that includes an instruction command. The e-mail is read through a communication controller, and a received case name confirmation unit and a sender verification unit examine the received e-mail to determine whether it is a control e-mail issued by an authorized sender. Thereafter, a command extraction unit extracts a control command from the e-mail. Upon receiving this command, an analysis controller controls the individual sections of an analysis unit.

Abstract: In a conventional evaluation method of IG effectivity on Cu in semiconductor silicon substrates, it is required to actually conduct the device process, or a great deal of time, manpower and expenses for manufacturing a MOS device for dielectric breakdown estimation and the like are needed, but in the present invention, the problem was solved by experimentally finding in advance the optimum ranges of the diagonal length and density of oxygen precipitates which make the IG effectivity on Cu favorable, and conducting a heat treatment for the addition of IG effectivity based on a simulation by calculations using Fokker-Planck equations so that the diagonal length and density of plate-like precipitates fall within the optimum ranges.

Abstract: In a conventional evaluation method of IG effectivity on Cu in semiconductor silicon substrates, it is required to actually conduct the device process, or a great deal of time, manpower and expenses for manufacturing a MOS device for dielectric breakdown estimation and the like are needed, but in the present invention, the problem was solved by experimentally finding in advance the optimum ranges of the diagonal length and density of oxygen precipitates which make the IG effectivity on Cu favorable, and conducting a heat treatment for the addition of IG effectivity based on a simulation by calculations using Fokker-Planck equations so that the diagonal length and density of plate-like precipitates fall within the optimum ranges.

Abstract: A scanner frame comprises a vertical track which is slidably attached at one end thereof to a horizontal track. The horizontal track is attached to a drawing board or any other suitable flat surface. An optical imaging device (i.e., an optical scanner) is slidably attached to the vertical track. A marker strip comprising a series of bars of uniform pitch are disposed on a surface of the horizontal track along the length thereof. These bars are detected by a sensor assembly disposed on the vertical track. Another marker strip comprising a series of bars of uniform pitch are disposed on a surface of the vertical track along the length thereof. These bars are detected by a sensor assembly disposed on the scanner. During use, a drawing to be scanned is secured on a board, the vertical track is positioned at the left-most position and the scanner is positioned at the upper end of the vertical track.