Abstract: Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed.

Abstract: A plug joint assembling apparatus (50) includes a joint bushing feed portion (100), a terminal temporary insertion portion (200), a terminal main insertion portion (300), a withstand voltage test portion (400), a terminal insertion condition check and talc coating portion (500), a first joint bushing extraction and supply mechanism (600), a second joint bushing extraction and supply mechanism (701), a third joint bushing extraction and supply mechanism (710), a fourth joint bushing extraction and supply mechanism (720), and a joint bushing extraction mechanism (730). These mechanisms (600, 701, 710, 720, 730) transport joint bushings. The joint bushing feed portion (100) includes a joint bushing check station (110) having a length measuring mechanism and an air vent hole detecting mechanism. The plug joint assembling apparatus (50) assembles plug joints efficiently at a stable pace by automatic assembly processes, stabilizes a check level, and improves reliability.

Abstract: In a pipeline burst EDO operation, a latency circuit 215 detects change of an internal column address strobe signal ZCASF from an active state to a non-active sate in the first cycle, and brings a signal OEMB into an active state. When a writing operation mode is specified, and an internal output enable signal ZOEF is in an active state, an output buffer control signal OEM attains an active state in response to the first activation edge of the internal column address strobe signal ZCASF after activation of the signal OEMB. Since the signal OEMB has already been in an active state in the first cycle of the signal ZCASF, a delay time for change of the signal OEM in response to activation of the signal ZCASF in the second cycle can be decreased.

Abstract: A semiconductor memory device includes four memory cell arrays, four output pads formed in a linear manner at the center of a semiconductor substrate, four output control circuits for generating readout data signals and control signals, four signal generation circuits responsive to the readout data signals for generating complementary pairs of data signals, and responsive to the control signals, four signal line groups including four signal lines connected between the output control circuits and the signal generation circuits, four output drivers responsive to pairs of data signals for supplying data to the output pads, and four signal line pairs connected between the signal generation circuits and output drivers. Signal generation circuits of great size are arranged at the center of the semiconductor substrate where the layout margin is great, and only the output driver is arranged in the proximity of the output pad where the layout margin is small. Therefore, the chip area is reduced.

Abstract: An image forming apparatus such as a printer or copier includes a photoreceptor for holding a latent image; a charger for charging the photoreceptor; an exposure unit such as an LED array for exposing the photoreceptor with light so as to form a latent image on the photoreceptor; and a developer placed in the vicinity of the photoreceptor, for developing the latent image with a developing agent so as to form a developing agent image on the photoreceptor. The developer includes a developing sleeve for holding the developing agent on its surface and a transferor for transferring the developing agent image on the photoreceptor to a recording medium. A cleaner is provided for cleaning a residual developing agent on the photoreceptor after the developing agent image is transferred to the recording medium and a purge control unit is provided for purging foreign matter from the developing agent on the developing sleeve.

Abstract: Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed.

Abstract: An image forming apparatus for forming a toner image. The apparatus includes: a photoreceptor drum, having a side surface and a circumferential surface, for forming an image on the circumferential surface: a driving means for driving the photoreceptor drum; a sliding member for decreasing steady state speed fluctuations of the photoreceptor drum; and an elastic member for pressing the sliding member onto the side surface of the photoreceptor drum.

Abstract: A DRAM device includes a read control circuit for inhibiting read out of one or more bits of a multi-bit data output from a plurality of memory cells in response to a bit designating signal for specifying the one or more bits. By arbitrarily setting the number of bits to be output from the DRAM device and combining that output with data from one or more additional memory devices, data of an arbitrary number of bits can be generated at a high speed.

Abstract: The constant current generating circuit includes a high resistance element for generating a very small current. This very small current is supplied to a first MOS transistor having a sufficiently large gate width to gate length ratio. The gate-source voltage of the first MOS transistor becomes its threshold voltage VTH, and the voltage applied across a resistance connected between the gate of the first MOS transistor and the ground line is set to a constant value VTH. Thus, a constant current is normally passed through the resistance. Since the very small current is supplied from the high resistance element which is normally turned on, regardless of the change of the power supply voltage, a constant current can be generated stably.

Abstract: Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed.

Abstract: A plurality of devices or memories, preferably dynamic random access memories (DRAMs), are used with their output terminals connected together, and the devices or DRAMs output data signals successively in response to externally applied output enable signals. A latch circuit is provided at the output terminal of each device or DRAM. The latch circuits hold not only the output signal of the DRAM to which it belongs but also the commonly connected output signal of another DRAM in response thereto. Consequently, the output signal from any one DRAM is held by the latch circuits until an output signal is provided from another DRAM. Thus, an accurate common output signal can be obtained without being affected by external noise or the requirement for extremely accurate timing signals.

Abstract: In a serial memory, data signal holding circuits for temporarily holding data read from memory cells are provided as a data register. One holding circuit includes a latch circuit and capacitors connected to input/output nodes of the latch circuit, respectively. The capacitors contribute to stabilizing the latch function by the latch circuit. Therefore, when transistors turn on in response to a serial selection signal at a high level, the latch circuit is prevented from being inverted by the potentials of a serial bus line pair. Accordingly, generation of reading errors is prevented.

Abstract: A dual port memory device capable of random access and serial access, having a random data input/output port arranged along a power supply wiring formed along one direction with respect to a power supply terminal, and a serial data input/output port arranged along a power supply wiring formed along the other direction with respect to the power supply terminal. Noise can be prevented from being included in a random data at an L level in inverting a serial data.

Abstract: Each driver circuit included in a word driver includes a transfer transistor and a driver transistor. A voltage of a predetermined voltage lower than a threshold voltage of the transfer transistor plus a power supply voltage is applied to the gate of the transfer transistor in an active period.

Abstract: An electrostatic recording apparatus having a transfer separation unit of a belt-roller transfer system wherein an endless-form transfer material conveyance belt is attached to a toner image retainer by an electrode roller and detached from the toner image retainer on the downstream side of the attached plane. A transfer material is passed through a gap between the transfer material conveyance belt and the electrode roller so that the toner image on the toner image retainer be transferred onto the transfer material.

Abstract: To prevent toner in a waste toner collection box incorporated in a process cartridge from becoming melted and solidified due to the heat generated by a fixing device positioned below the waste toner collection box, a duct is provided therebetween. The duct may be integrally provided below the waste toner collection box or above the fixing device. A fan, which faces one end of the duct, moves the air therein. One or both ends of the duct may be provided with a handle, which also serves as a wide mouthed extension to the duct.

Abstract: A semiconductor delay device is disclosed which allows a delay time to be fixed irrespective of a power supply voltage. The semiconductor delay device includes a first switching circuit, a second switching circuit, a capacitor an N channel transistor and a control voltage generation circuit. The first switching circuit switches in response to an input signal. The capacitor is charged and discharged in response to an output of the first switching circuit. The second switching circuit switches when a voltage level of the capacitor exceeds a fixed voltage. The control voltage generation circuit generates a voltage signal appropriately proportional to a square root of the power supply voltage and applies the generated voltage signal to a gate of an N channel transistor. The N channel transistor is connected between the first switching circuit and the source and current drivability of which is changed in response to the voltage signal. As a result, a delay time can be fixed irrespective of a power supply voltage.

Abstract: A transfer device of the type having a belt which is stretched around a driving roller and an electric potential-applied driven roller, whereby the transfer device transfers a toner image from an image carrier onto a recording paper, and conveys the recording paper. The cleaning device is positioned so that its blade contacts the belt at a point a little downstream of the point where the belt separates from the driving roller.

Abstract: A voltage amplifier comprises a pair of bit lines (B1, B2) connected to a dummy cell and a plurality of memory cells; a pair of n channel MOS transistors (Q1, Q2) connected between the pair of bit lines and an I/O line each operating in response to the potential of the other bit line; and a pair of p channel MOS transistors (Q5, Q6) connected between the pair of n channel MOS transistors (Q1, Q2) and the bit lines (B1, B2) operating in response to the ground potential. As the voltage difference of the pair of bit lines is amplified, the p channel MOS transistor connected to the bit line held at the lower potential turns on, and the connection between the bit line and the n channel MOS transistor is cut off.

Abstract: A circuit (50) is provided in a dynamic RAM (1) for detecting establishment of a substrate bias voltage (V.sub.BB) when the power is first turned on. A NAND gate (5d) in a clock generator circuit (10) immediately applies a high level signal to an inner circuit (11) when the power is turned on. Successively, the NAND gate (5d) applies a RAS signal to the inner circuit (11) in response to the establishment of V.sub.BB. Therefore, the dynamic RAM (1) is brought to a standby state immediately after the power is turned on and thereafter is controlled by the RAS signal. Consequently, flow of excessive current and latch-up immediately after the power is turned on can be prevented.