Patents by Inventor Takayuki Oshima

Takayuki Oshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190252672
    Abstract: Provided is a lithium secondary battery having a nonaqueous electrolyte which contains at least one compound selected from the group consisting of monofluorophosphoric acid salts, and difluorophosphoric acid salts, in an amount of 10 ppm or more of the whole nonaqueous electrolyte, and a negative electrode selected from [1], [2], [3] and [6]: [1]: a negative electrode containing two or more carbonaceous substances differing in crystallinity; [2]: a negative electrode containing an amorphous carbonaceous substance which, when examined by wide-angle X-ray diffractometry, has an interplanar spacing (d002) for the (002) planes of 0.337 nm or larger and a crystallite size (Lc) of 80 nm or smaller and which, in an examination by argon ion laser Raman spectroscopy, has a Raman. R value of 0.
    Type: Application
    Filed: April 25, 2019
    Publication date: August 15, 2019
    Applicant: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Hidekazu MIYAGI, Ryoichi KATO, Masakazu YOKOMIZO, Hiroyuki UONO, Hitoshi MATSUMOTO, Tomohiro SATOU, Minoru KOTATO, Takayuki NAKAJIMA, Hitoshi SUZUKI, Hiroyuki OSHIMA
  • Patent number: 10381192
    Abstract: In one embodiment, an ion implantation apparatus includes an ion source configured to generate an ion beam. The apparatus further includes a scanner configured to change an irradiation position with the ion beam on an irradiation target. The apparatus further includes a first electrode configured to accelerate an ion in the ion beam. The apparatus further includes a controller configured to change at least any of energy and an irradiation angle of the ion beam according to the irradiation position by controlling the ion beam having been generated from the ion source.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: August 13, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsuyoshi Fujii, Takayuki Ito, Yasunori Oshima
  • Publication number: 20190244855
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Application
    Filed: April 16, 2019
    Publication date: August 8, 2019
    Inventors: Junji NOGUCHI, Takayuki OSHIMA, Noriko MIURA, Kensuke ISHIKAWA, Tomio IWASAKI, Kiyomi KATSUYAMA, Tatsuyuki SAITO, Tsuyoshi TAMARU, Hizuru YAMAGUCHI
  • Patent number: 10304726
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: May 28, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
  • Publication number: 20190035678
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Application
    Filed: September 21, 2018
    Publication date: January 31, 2019
    Inventors: Junji NOGUCHI, Takayuki OSHIMA, Noriko MIURA, Kensuke ISHIKAWA, Tomio IWASAKI, Kiyomi KATSUYAMA, Tatsuyuki SAITO, Tsuyoshi TAMARU, Hizuru YAMAGUCHI
  • Patent number: 10170415
    Abstract: On a transistor layer having arranged thereon multiple transistors each including a drain, a source, and a gate, metal interconnection layers serving as input side interconnection layers connected to the drains of the respective transistors and metal interconnection layers serving as output side interconnection layers connected to the sources of the respective transistors are arranged in parallel. Also provided are a plurality of through holes connecting the metal interconnection layers serving as input side interconnection layers to the drains of the respective transistors and connecting the metal interconnection layers serving as output side interconnection layers to the sources of the respective transistors. Resistance values of the plurality of through holes are changed along an arranging direction of the input side interconnection layers and the output side interconnection layers. Accordingly, current densities of the transistors arranged to be distributed in a two-dimensional manner can be uniform.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: January 1, 2019
    Assignee: Hitachi Automotive Systems, Inc.
    Inventors: Katsumi Ikegaya, Takayuki Oshima
  • Patent number: 10121693
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: November 6, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
  • Publication number: 20180247892
    Abstract: On a transistor layer having arranged thereon multiple transistors each including a drain, a source, and a gate, metal interconnection layers serving as input side interconnection layers connected to the drains of the respective transistors and metal interconnection layers serving as output side interconnection layers connected to the sources of the respective transistors are arranged in parallel. Also provided are a plurality of through holes connecting the metal interconnection layers serving as input side interconnection layers to the drains of the respective transistors and connecting the metal interconnection layers serving as output side interconnection layers to the sources of the respective transistors. Resistance values of the plurality of through holes are changed along an arranging direction of the input side interconnection layers and the output side interconnection layers. Accordingly, current densities of the transistors arranged to be distributed in a two-dimensional manner can be uniform.
    Type: Application
    Filed: July 25, 2016
    Publication date: August 30, 2018
    Applicant: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Katsumi IKEGAYA, Takayuki OSHIMA
  • Publication number: 20180218936
    Abstract: It is an object of the present invention to provide a switch element and a load driving apparatus capable of suppressing a characteristic change of an on-resistance without lowering an off-breakdown voltage. The switching element includes a control electrode, an active element region, and an inactive element region, and the active element region and the inactive element region are formed adjacent to each other on the control electrode. Alternatively, in the load driving apparatus including a current driving switch element and a current detecting switch element that is connected in parallel to the load driving switch element and that detects an energization current of the load driving switch element, the current detecting switch element includes at least a control electrode, an active element region, and an inactive element region, and the active element region and the inactive element region are formed adjacent to each other on the control electrode.
    Type: Application
    Filed: July 1, 2016
    Publication date: August 2, 2018
    Inventors: Shinichirou WADA, Takayuki OSHIMA, Katsumi IKEGAYA
  • Publication number: 20180211898
    Abstract: Provided is a vehicle-mounted semiconductor device enabling a temperature increase of active elements to be restricted. A vehicle-mounted semiconductor device includes: a semiconductor substrate; a plurality of active elements formed on the semiconductor substrate; a plurality of trenches surrounding the plurality of active elements to insulate and separate the active elements; and a terminal connecting in parallel the plurality of active elements insulated and separated by different trenches among the plurality of trenches and connected to an outside.
    Type: Application
    Filed: August 2, 2016
    Publication date: July 26, 2018
    Inventors: Takayuki OSHIMA, Shinichirou WADA, Katsumi IKEGAYA, Hiroshi YONEDA
  • Publication number: 20180047620
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Application
    Filed: October 9, 2017
    Publication date: February 15, 2018
    Inventors: Junji NOGUCHI, Takayuki OSHIMA, Noriko MIURA, Kensuke ISHIKAWA, Tomio IWASAKI, Kiyomi KATSUYAMA, Tatsuyuki SAITO, Tsuyoshi TAMARU, Hizuru YAMAGUCHI
  • Patent number: 9818639
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: November 14, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
  • Publication number: 20170200637
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Application
    Filed: March 27, 2017
    Publication date: July 13, 2017
    Inventors: Junji NOGUCHI, Takayuki OSHIMA, Noriko MIURA, Kensuke ISHIKAWA, Tomio IWASAKI, Kiyomi KATSUYAMA, Tatsuyuki SAITO, Tsuyoshi TAMARU, Hizuru YAMAGUCHI
  • Patent number: 9659867
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: May 23, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
  • Publication number: 20170011994
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Application
    Filed: September 22, 2016
    Publication date: January 12, 2017
    Inventors: Junji NOGUCHI, Takayuki OSHIMA, Noriko MIURA, Kensuke ISHIKAWA, Tomio IWASAKI, Kiyomi KATSUYAMA, Tatsuyuki SAITO, Tsuyoshi TAMARU, Hizuru YAMAGUCHI
  • Patent number: 9490213
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: November 8, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
  • Patent number: 9293578
    Abstract: Adverse effects can be hardly exerted on a current performance of an LDMOSFET to suppress the amount of carrier implantation from an anode layer of an LDMOS parasitic diode, and improve a reverse recovery withstand of the parasitic diode. The LDMOSFET includes a semiconductor substrate having a first semiconductor region formed of a feeding region of a first conductivity type at a position where a field oxide film is not present on a surface layer of a semiconductor region in which the field oxide film is selectively formed, and a second semiconductor region formed of a well region of a second conductivity type which is an opposite conductivity type, and feeding regions of the first conductivity type and the second conductivity type formed on an upper layer of the well region, and a gate electrode that faces the well region through a gate oxide film.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: March 22, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Tomoyuki Miyoshi, Takayuki Oshima, Yohei Yanagida, Hiroki Kimura, Kenji Miyakoshi
  • Publication number: 20150235962
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Application
    Filed: May 1, 2015
    Publication date: August 20, 2015
    Inventors: Junji NOGUCHI, Takayuki OSHIMA, Noriko MIURA, Kensuke ISHIKAWA, Tomio IWASAKI, Kiyomi KATSUYAMA, Tatsuyuki SAITO, Tsuyoshi TAMARU, Hizuru YAMAGUCHI
  • Patent number: 9064870
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: June 23, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
  • Publication number: 20140312499
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Application
    Filed: June 30, 2014
    Publication date: October 23, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Junji NOGUCHI, Takayuki OSHIMA, Noriko MIURA, Kensuke ISHIKAWA, Tomio IWASAKI, Kiyomi KATSUYAMA, Tatsuyuki SAITO, Tsuyoshi TAMARU, Hizuru YAMAGUCHI