Patents by Inventor Takayuki Oshima

Takayuki Oshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200211745
    Abstract: An object is to provide a new electronic control unit that can improve detection accuracy of a sense current even in a region where the current value of the sense current is small. Provided is a sense current detection unit including a plurality of sense transistors that have different current flow rates and that are connected to current output transistors controlling a current flowing in a coil load. The current in the sense current detection unit is input to an analog/digital converter, and the current value of the current flowing in the sense current detection unit is converted into a digital value. The current value of the current flowing in the sense current detection unit is increased through a combination or a selection of the plurality of sense transistors of the sense current detection unit in a region where the current value of the main current of the current output transistors is small compared to a region where the current value of the main current is large.
    Type: Application
    Filed: April 19, 2018
    Publication date: July 2, 2020
    Inventors: Katsumi IKEGAYA, Keishi KOMORIYAMA, Yoshiaki MIZUHASHI, Takayuki OSHIMA, Shinichirou WADA
  • Patent number: 10665496
    Abstract: It is an object of the present invention to provide a switch element and a load driving apparatus capable of suppressing a characteristic change of an on-resistance without lowering an off-breakdown voltage. The switching element includes a control electrode, an active element region, and an inactive element region, and the active element region and the inactive element region are formed adjacent to each other on the control electrode. Alternatively, in the load driving apparatus including a current driving switch element and a current detecting switch element that is connected in parallel to the load driving switch element and that detects an energization current of the load driving switch element, the current detecting switch element includes at least a control electrode, an active element region, and an inactive element region, and the active element region and the inactive element region are formed adjacent to each other on the control electrode.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: May 26, 2020
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Shinichirou Wada, Takayuki Oshima, Katsumi Ikegaya
  • Publication number: 20200157289
    Abstract: Disclosed is a production method for a poly(vinyl alcohol) having a degree of saponification of 97.0 mol % or more, comprising: a pulverization step of pulverizing a first poly(vinyl alcohol) having a particulate form to obtain a second poly(vinyl alcohol) having an adjusted particle size, and a heating step of heating the second poly(vinyl alcohol).
    Type: Application
    Filed: July 10, 2017
    Publication date: May 21, 2020
    Applicant: DENKA COMPANY LIMITED
    Inventors: Shin SUGIMURA, Takayuki OSHIMA
  • Publication number: 20200119257
    Abstract: Provided is a method of manufacturing a piezoelectric element in which, at a time when the piezoelectric element is manufactured, a piezoelectric material is prevented from being exposed to a temperature higher than a Curie temperature thereof to be depolarized, to thereby significantly decrease piezoelectric properties. The method of manufacturing a piezoelectric element includes a first step of arranging a plurality of electrodes on a piezoelectric material, electrically short-circuiting two or more electrodes of the plurality of electrodes, and subjecting the piezoelectric material to heat treatment, and a second step of, after the first step, electrically opening the short circuit of the two or more electrodes at a time when a temperature of the piezoelectric material decreases to less than a temperature of the piezoelectric material at a time of the heat treatment.
    Type: Application
    Filed: March 1, 2018
    Publication date: April 16, 2020
    Inventors: Akira Uebayashi, Tatsuo Furuta, Kanako Oshima, Takayuki Watanabe, Jumpei Hayashi, Satoshi Fujita, Yuki Iitsuka
  • Publication number: 20200113490
    Abstract: A measurement unit is attached to a measurement target person and measures an acceleration. A body motion calculation unit obtains the magnitude of a body motion of the measurement target person based on the acceleration measured by the measurement unit. An activity state determination unit time-serially obtains an activity state representing whether the measurement target person is in a first state or a second state, based on a posture decided by a posture decision unit and the magnitude of the body motion calculated by the body motion calculation unit. If the activity state after continues for a predetermined time defined in advance, an activity state correction unit determines that the transition of the activity state obtained by the activity state determination unit has been done. A time correction unit returns the transition time of the activity state determined by the activity state correction unit.
    Type: Application
    Filed: January 22, 2018
    Publication date: April 16, 2020
    Inventors: Takayuki OGASAWARA, Shingo TSUKADA, Shoichi OSHIMA, Hiroki MORIMURA, Hiroshi NAKASHIMA, Rieko SATO
  • Patent number: 10424634
    Abstract: In a semiconductor device, a source and a drain layers are located in a surface region of a substrate. A source crystal layer is located in a contact region of the source layer to extend to a position higher than the substrate. A drain crystal layer is located in a contact region of the drain layer to extend to a position higher than the substrate. A source contact is located on the source crystal layer. A drain contact is located on the drain crystal layer. A gate width or a gate length extends to a crystal orientation <110> of the substrate. A long side or a major axis of the source crystal layer or a long side or a major axis of the drain crystal layer extends in a direction inclined with respect to the crystal orientation <110> in a planar layout parallel to the surface of the substrate.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: September 24, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yasunori Oshima, Takayuki Ito
  • Publication number: 20190280084
    Abstract: In a semiconductor device, a source and a drain layers are located in a surface region of a substrate. A source crystal layer is located in a contact region of the source layer to extend to a position higher than the substrate. A drain crystal layer is located in a contact region of the drain layer to extend to a position higher than the substrate. A source contact is located on the source crystal layer. A drain contact is located on the drain crystal layer. A gate width or a gate length extends to a crystal orientation <110> of the substrate. A long side or a major axis of the source crystal layer or a long side or a major axis of the drain crystal layer extends in a direction inclined with respect to the crystal orientation <110> in a planar layout parallel to the surface of the substrate.
    Type: Application
    Filed: July 19, 2018
    Publication date: September 12, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yasunori OSHIMA, Takayuki ITO
  • Publication number: 20190252672
    Abstract: Provided is a lithium secondary battery having a nonaqueous electrolyte which contains at least one compound selected from the group consisting of monofluorophosphoric acid salts, and difluorophosphoric acid salts, in an amount of 10 ppm or more of the whole nonaqueous electrolyte, and a negative electrode selected from [1], [2], [3] and [6]: [1]: a negative electrode containing two or more carbonaceous substances differing in crystallinity; [2]: a negative electrode containing an amorphous carbonaceous substance which, when examined by wide-angle X-ray diffractometry, has an interplanar spacing (d002) for the (002) planes of 0.337 nm or larger and a crystallite size (Lc) of 80 nm or smaller and which, in an examination by argon ion laser Raman spectroscopy, has a Raman. R value of 0.
    Type: Application
    Filed: April 25, 2019
    Publication date: August 15, 2019
    Applicant: MITSUBISHI CHEMICAL CORPORATION
    Inventors: Hidekazu MIYAGI, Ryoichi KATO, Masakazu YOKOMIZO, Hiroyuki UONO, Hitoshi MATSUMOTO, Tomohiro SATOU, Minoru KOTATO, Takayuki NAKAJIMA, Hitoshi SUZUKI, Hiroyuki OSHIMA
  • Patent number: 10381192
    Abstract: In one embodiment, an ion implantation apparatus includes an ion source configured to generate an ion beam. The apparatus further includes a scanner configured to change an irradiation position with the ion beam on an irradiation target. The apparatus further includes a first electrode configured to accelerate an ion in the ion beam. The apparatus further includes a controller configured to change at least any of energy and an irradiation angle of the ion beam according to the irradiation position by controlling the ion beam having been generated from the ion source.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: August 13, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsuyoshi Fujii, Takayuki Ito, Yasunori Oshima
  • Publication number: 20190244855
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Application
    Filed: April 16, 2019
    Publication date: August 8, 2019
    Inventors: Junji NOGUCHI, Takayuki OSHIMA, Noriko MIURA, Kensuke ISHIKAWA, Tomio IWASAKI, Kiyomi KATSUYAMA, Tatsuyuki SAITO, Tsuyoshi TAMARU, Hizuru YAMAGUCHI
  • Patent number: 10304726
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: May 28, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
  • Publication number: 20190035678
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Application
    Filed: September 21, 2018
    Publication date: January 31, 2019
    Inventors: Junji NOGUCHI, Takayuki OSHIMA, Noriko MIURA, Kensuke ISHIKAWA, Tomio IWASAKI, Kiyomi KATSUYAMA, Tatsuyuki SAITO, Tsuyoshi TAMARU, Hizuru YAMAGUCHI
  • Patent number: 10170415
    Abstract: On a transistor layer having arranged thereon multiple transistors each including a drain, a source, and a gate, metal interconnection layers serving as input side interconnection layers connected to the drains of the respective transistors and metal interconnection layers serving as output side interconnection layers connected to the sources of the respective transistors are arranged in parallel. Also provided are a plurality of through holes connecting the metal interconnection layers serving as input side interconnection layers to the drains of the respective transistors and connecting the metal interconnection layers serving as output side interconnection layers to the sources of the respective transistors. Resistance values of the plurality of through holes are changed along an arranging direction of the input side interconnection layers and the output side interconnection layers. Accordingly, current densities of the transistors arranged to be distributed in a two-dimensional manner can be uniform.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: January 1, 2019
    Assignee: Hitachi Automotive Systems, Inc.
    Inventors: Katsumi Ikegaya, Takayuki Oshima
  • Patent number: 10121693
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: November 6, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
  • Publication number: 20180247892
    Abstract: On a transistor layer having arranged thereon multiple transistors each including a drain, a source, and a gate, metal interconnection layers serving as input side interconnection layers connected to the drains of the respective transistors and metal interconnection layers serving as output side interconnection layers connected to the sources of the respective transistors are arranged in parallel. Also provided are a plurality of through holes connecting the metal interconnection layers serving as input side interconnection layers to the drains of the respective transistors and connecting the metal interconnection layers serving as output side interconnection layers to the sources of the respective transistors. Resistance values of the plurality of through holes are changed along an arranging direction of the input side interconnection layers and the output side interconnection layers. Accordingly, current densities of the transistors arranged to be distributed in a two-dimensional manner can be uniform.
    Type: Application
    Filed: July 25, 2016
    Publication date: August 30, 2018
    Applicant: HITACHI AUTOMOTIVE SYSTEMS, LTD.
    Inventors: Katsumi IKEGAYA, Takayuki OSHIMA
  • Publication number: 20180218936
    Abstract: It is an object of the present invention to provide a switch element and a load driving apparatus capable of suppressing a characteristic change of an on-resistance without lowering an off-breakdown voltage. The switching element includes a control electrode, an active element region, and an inactive element region, and the active element region and the inactive element region are formed adjacent to each other on the control electrode. Alternatively, in the load driving apparatus including a current driving switch element and a current detecting switch element that is connected in parallel to the load driving switch element and that detects an energization current of the load driving switch element, the current detecting switch element includes at least a control electrode, an active element region, and an inactive element region, and the active element region and the inactive element region are formed adjacent to each other on the control electrode.
    Type: Application
    Filed: July 1, 2016
    Publication date: August 2, 2018
    Inventors: Shinichirou WADA, Takayuki OSHIMA, Katsumi IKEGAYA
  • Publication number: 20180211898
    Abstract: Provided is a vehicle-mounted semiconductor device enabling a temperature increase of active elements to be restricted. A vehicle-mounted semiconductor device includes: a semiconductor substrate; a plurality of active elements formed on the semiconductor substrate; a plurality of trenches surrounding the plurality of active elements to insulate and separate the active elements; and a terminal connecting in parallel the plurality of active elements insulated and separated by different trenches among the plurality of trenches and connected to an outside.
    Type: Application
    Filed: August 2, 2016
    Publication date: July 26, 2018
    Inventors: Takayuki OSHIMA, Shinichirou WADA, Katsumi IKEGAYA, Hiroshi YONEDA
  • Publication number: 20180047620
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Application
    Filed: October 9, 2017
    Publication date: February 15, 2018
    Inventors: Junji NOGUCHI, Takayuki OSHIMA, Noriko MIURA, Kensuke ISHIKAWA, Tomio IWASAKI, Kiyomi KATSUYAMA, Tatsuyuki SAITO, Tsuyoshi TAMARU, Hizuru YAMAGUCHI
  • Patent number: 9818639
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: November 14, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Junji Noguchi, Takayuki Oshima, Noriko Miura, Kensuke Ishikawa, Tomio Iwasaki, Kiyomi Katsuyama, Tatsuyuki Saito, Tsuyoshi Tamaru, Hizuru Yamaguchi
  • Publication number: 20170200637
    Abstract: The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.
    Type: Application
    Filed: March 27, 2017
    Publication date: July 13, 2017
    Inventors: Junji NOGUCHI, Takayuki OSHIMA, Noriko MIURA, Kensuke ISHIKAWA, Tomio IWASAKI, Kiyomi KATSUYAMA, Tatsuyuki SAITO, Tsuyoshi TAMARU, Hizuru YAMAGUCHI