Patents by Inventor Takayuki Oshima

Takayuki Oshima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020008992
    Abstract: The present invention proposes a non-volatile semiconductor storage, comprising a plurality of main bit lines, a plurality of sub bit lines connected to the main bit lines, and a plurality of memory cell arrays, each including a plurality of non-volatile semiconductor memory cells disposed like an array. Each of those memory cells has a source terminal, a drain terminal, and a control gate, and each source-drain path is connected to a sub bit line. Between a main bit line and a sub bit line connected to the main bit line is disposed the source-drain path of a first transistor, and the source-drain path of a second transistor is connected to the sub bit line.
    Type: Application
    Filed: September 14, 2001
    Publication date: January 24, 2002
    Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Kazuyoshi Shiba, Kazufumi Suzukawa, Masamichi Fujito, Takayuki Oshima, Sonoko Abe, Kiyoshi Matsubara
  • Patent number: 6340632
    Abstract: Insulating films 34 through 38 (of which insulating films 34, 36, 38 are silicon nitride films and insulating films 35, 38 are silicon oxide films) are sequentially formed on the wires 33 of the fourth wiring layer and groove pattern 40 is transferred into the insulating film 38 by means of photolithography. An anti-reflection film 41 is formed to fill the grooves 40 of the insulating film 38 and then a resist film 42 carrying a hole pattern 43 is formed. The films are subjected to an etching operation in the presence of the resist film 42 to transfer the hole pattern into the insulating films 38, 37, 36 and part of the insulating film 35. Subsequently, the resist film 42 and the anti-reflection film 41 are removed and the groove pattern 40 and the hole pattern 43 are transferred respectively into the insulating film 37 and the insulating film 35 by using the insulating film 38 as mask.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: January 22, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Shinichi Fukada, Kazuo Nojiri, Takashi Yunogami, Shoji Hotta, Hideo Aoki, Takayuki Oshima, Nobuyoshi Kobayashi
  • Patent number: 6307780
    Abstract: The present invention proposes a non-volatile semiconductor storage, comprising a plurality of main bit lines, a plurality of sub bit lines connected to the main bit lines, and a plurality of memory cell arrays, each including a plurality of non-volatile semiconductor memory cells disposed like an array. Each of those memory cells has a source terminal, a drain terminal, and a control gate, and each source-drain path is connected to a sub bit line. Between a main bit line and a sub bit line connected to the main bit line is disposed the source-drain path of a first transistor, and the source-drain path of a second transistor is connected to the sub bit line.
    Type: Grant
    Filed: July 27, 2000
    Date of Patent: October 23, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Kazuyoshi Shiba, Kazufumi Suzukawa, Masamichi Fujito, Takayuki Oshima, Sonoko Abe, Kiyoshi Matsubara
  • Patent number: 6266978
    Abstract: A simple method for producing a synthetic quartz glass having excellent homogeneity and high transmittance, which is useful as an optical material in producing steppers equipped with an ArF excimer laser as a radiation source. A method for producing a synthetic quartz glass for use in ArF excimer laser lithography, which comprises irradiating a highly homogeneous synthetic quartz glass containing less than 60 ppb of Na with ultraviolet radiation having a maximum wavelength of 260 nm for not less than the duration expressed by the equation: Y=(80X−1880)/Z wherein X represents an Na concentration (ppb), Y represents the duration of irradiation (hours), and Z represents the illuminance of an ultraviolet radiation on an irradiated surface (mW/cm2).
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: July 31, 2001
    Assignees: Heraeus Quarzglas GmbH, Shin-Etsu Quartz Products Co., Ltd.
    Inventors: Takayuki Oshima, Akira Fujinoki, Hiroyuki Nishimura, Yasuyuki Yaginuma
  • Patent number: 6122196
    Abstract: The present invention proposes a non-volatile semiconductor storage, comprising a plurality of main bit lines, a plurality of sub bit lines connected to the main bit lines, and a plurality of memory cell arrays, each including a plurality of non-volatile semiconductor memory cells disposed like an array. Each of those memory cells has a source terminal, a drain terminal, and a control gate, and each source-drain path is connected to a sub bit line. Between a main bit line and a sub bit line connected to the main bit line is disposed the source-drain path of a first transistor, and the source-drain path of a second transistor is connected to the sub bit line.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: September 19, 2000
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Toshihiro Tanaka, Yutaka Shinagawa, Kazuyoshi Shiba, Kazufumi Suzukawa, Masamichi Fujito, Takayuki Oshima, Sonoko Abe, Kiyoshi Matsubara