Patents by Inventor Takayuki Saiki
Takayuki Saiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8547773Abstract: An integrated circuit device includes at least one data driver block for driving data lines, a plurality of control transistors TC1 and TC2, each of the control transistors being provided corresponding to each output line of the data driver block and controlled by using a common control signal, and a pad arrangement region in which data driver pads P1 and P2 for electrically connecting the data lines and the output lines QL1 and QL2 of the data driver block are disposed. The control transistors TC1 and TC2 are disposed in the pad arrangement region.Type: GrantFiled: June 30, 2006Date of Patent: October 1, 2013Assignee: Seiko Epson CorporationInventors: Takayuki Saiki, Satoru Ito, Masahiko Moriguchi, Takashi Kumagai, Hisanobu Ishiyama, Takashi Fujise, Junichi Karasawa, Satoru Kodaira, Kazuhiro Maekawa
-
Patent number: 8338890Abstract: A semiconductor device includes: a plurality of external terminals; a plurality of semiconductor substrates that are layered; a through electrode penetrating through at least one of the semiconductor substrates and electrically connected with any of the external terminals; and a plurality of electrostatic discharge protection circuits provided on any one of the semiconductor substrates. In the device, the through electrode is electrically connected with the plurality of electrostatic discharge protection circuits.Type: GrantFiled: November 30, 2009Date of Patent: December 25, 2012Assignee: Seiko Epson CorporationInventors: Takayuki Saiki, Shinya Sato, Hiroyuki Takamiya
-
Patent number: 8310478Abstract: An integrated circuit device includes first and second transistors NTr1 and PTr1 push-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node ND by a charge-pump operation, and a pad PD electrically connected with the connection node ND and electrically connected with a flying capacitor, to which a given voltage is applied at one end, at the other end of the flying capacitor. The pad PD is disposed in an upper layer of at least one of the first and second transistors NTr1 and PTr1 so that the pad PD overlaps part or the entirety of at least one of the first and second transistors NTr1 and PTr1.Type: GrantFiled: June 30, 2006Date of Patent: November 13, 2012Assignee: Seiko Epson CorporationInventors: Takashi Kumagai, Hisanobu Ishiyama, Kazuhiro Maekawa, Satoru Ito, Takashi Fujise, Junichi Karasawa, Satoru Kodaira, Takayuki Saiki, Hiroyuki Takamiya
-
Patent number: 8247841Abstract: A semiconductor device includes: a plurality of semiconductor substrates that are layered; a through electrode penetrating through a predetermined semiconductor substrate of the semiconductor substrates and electrically connected with an external terminal of the semiconductor device; a circuit element provided on the predetermined semiconductor substrate; and an electrostatic discharge protection circuit also provided on the predetermined semiconductor substrate. In the device, wiring resistance between the electrostatic discharge protection circuit and the through electrode is smaller than wiring resistance between the circuit element and the through electrode.Type: GrantFiled: November 30, 2009Date of Patent: August 21, 2012Assignee: Seiko Epson CorporationInventors: Takayuki Saiki, Shinya Sato, Hiroyuki Takamiya
-
Patent number: 8188544Abstract: An integrated circuit device includes a pad PDx and an electrostatic discharge protection element ESDx formed in a rectangular region and electrically connected with the pad PDx. The pad PDx is disposed in an upper layer of the electrostatic discharge protection element ESDx so that an arrangement direction of the pads is parallel to a long side direction of the region in which the electrostatic discharge protection element ESDx is formed, and the pad PDx overlaps part or the entirety of the electrostatic discharge protection element ESDx.Type: GrantFiled: June 30, 2006Date of Patent: May 29, 2012Assignee: Seiko Epson CorporationInventors: Takashi Kumagai, Hisanobu Ishiyama, Kazuhiro Maekawa, Satoru Ito, Takashi Fujise, Junichi Karasawa, Satoru Kodaira, Takayuki Saiki, Hiroyuki Takamiya
-
Patent number: 8188545Abstract: A semiconductor integrated circuit includes N pad rows in which pads are respectively arranged, and electrostatic discharge protection elements disposed in a lower layer of the N pad rows and connected with each pad in the N pad rows. The electrostatic discharge protection elements are disposed in a lower layer of regions at least partially including each of the N pads.Type: GrantFiled: February 8, 2007Date of Patent: May 29, 2012Assignee: Seiko Epson CorporationInventors: Takayuki Saiki, Satoru Ito, Masahiko Moriguchi
-
Patent number: 8076748Abstract: A semiconductor device is provided having a high performance resistance element. In an N-type well isolated by an insulating film, two higher concentration N-type regions are formed. An interlayer insulating film is also formed. In a plurality of openings in the interlayer insulating film, one electrode group having a plurality of electrodes is formed on one N-type region, while a second electrode group having a plurality of electrodes is formed on the other N-type region. The relationship between the two N-type regions is between an island region and an annular region surrounding the island. The annular region of the N-type well between the island region and the annular region serves as a resistor R. Thus, discharge channels for charges applied excessively because of ESD or the like evenly exist in the periphery (four regions) of the one N-type region.Type: GrantFiled: May 23, 2008Date of Patent: December 13, 2011Assignee: Seiko Epson CorporationInventors: Takayuki Saiki, Kazuhiko Okawa
-
Patent number: 7974051Abstract: An interface circuit is provided between a first circuit block and a second circuit block that operates using a power supply system differing from that of the first circuit block. An electrostatic discharge protection circuit that include a PN diode and a diffused resistor is formed in order to prevent electrostatic discharge destruction of a gate insulating film of a transistor that forms the interface circuit. The electrostatic discharge protection circuit may be formed using the remaining basic cells of a gate array that forms the second circuit block. An electrostatic discharge protection circuit formed of a bidirectional diode may be connected between a first low-potential power supply and a second low-potential power supply.Type: GrantFiled: April 9, 2008Date of Patent: July 5, 2011Assignee: Seiko Epson CorporationInventors: Shinya Sato, Takayuki Saiki, Hiroyuki Takamiya
-
Publication number: 20110128274Abstract: An integrated circuit device includes first and second transistors NTr1 and PTr1 push-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node ND by a charge-pump operation, and a pad PD electrically connected with the connection node ND and electrically connected with a flying capacitor, to which a given voltage is applied at one end, at the other end of the flying capacitor. The pad PD is disposed in an upper layer of at least one of the first and second transistors NTr1 and PTr1 so that the pad PD overlaps part or the entirety of at least one of the first and second transistors NTr1 and PTr1.Type: ApplicationFiled: February 8, 2011Publication date: June 2, 2011Applicant: SEIKO EPSON CORPORATIONInventors: Takashi Kumagai, Hisanobu Ishiyama, Kazuhiro Maekawa, Satoru ITO, Takashi Fujise, Junichi Karasawa, Satoru Kodaira, Takayuki Saiki, Hiroyuki Takamiya
-
Publication number: 20100133678Abstract: A semiconductor device includes: a plurality of semiconductor substrates that are layered; a through electrode penetrating through a predetermined semiconductor substrate of the semiconductor substrates and electrically connected with an external terminal of the semiconductor device; a circuit element provided on the predetermined semiconductor substrate; and an electrostatic discharge protection circuit also provided on the predetermined semiconductor substrate. In the device, wiring resistance between the electrostatic discharge protection circuit and the through electrode is smaller than wiring resistance between the circuit element and the through electrode.Type: ApplicationFiled: November 30, 2009Publication date: June 3, 2010Applicant: SEIKO EPSON CORPORATIONInventors: Takayuki SAIKI, Shinya SATO, Hiroyuki TAKAMIYA
-
Publication number: 20100133701Abstract: A semiconductor device includes: a plurality of external terminals; a plurality of semiconductor substrates that are layered; a through electrode penetrating through at least one of the semiconductor substrates and electrically connected with any of the external terminals; and a plurality of electrostatic discharge protection circuits provided on any one of the semiconductor substrates. In the device, the through electrode is electrically connected with the plurality of electrostatic discharge protection circuits.Type: ApplicationFiled: November 30, 2009Publication date: June 3, 2010Applicant: SEIKO EPSON CORPORATIONInventors: Takayuki SAIKI, Shinya SATO, Hiroyuki TAKAMIYA
-
Publication number: 20080253045Abstract: An interface circuit is provided between a first circuit block and a second circuit block that operates using a power supply system differing from that of the first circuit block. An electrostatic discharge protection circuit that include a PN diode and a diffused resistor is formed in order to prevent electrostatic discharge destruction of a gate insulating film of a transistor that forms the interface circuit. The electrostatic discharge protection circuit may be formed using the remaining basic cells of a gate array that forms the second circuit block. An electrostatic discharge protection circuit formed of a bidirectional diode may be connected between a first low-potential power supply and a second low-potential power supply.Type: ApplicationFiled: April 9, 2008Publication date: October 16, 2008Applicant: SEIKO EPSON CORPORATIONInventors: Shinya SATO, Takayuki SAIKI, Hiroyuki TAKAMIYA
-
Publication number: 20080252634Abstract: An integrated circuit device includes a first circuit block that includes low-voltage transistors (LVTr) and operates using a first high-potential power supply voltage and a first low-potential power supply voltage, a second circuit block that includes low-voltage transistors (LVTr) and operates using a second high-potential power supply voltage and a second low-potential power supply voltage that differ in power supply system from the first circuit block, and an interface circuit (I/O buffer) provided between the first circuit block and the second circuit block. The interface circuit (I/O buffer) includes medium-voltage transistors (MVTr: transistors of which the thickness of the gate insulating film is larger than that of the low-voltage transistors (LVTr)). An electrostatic discharge protection circuit formed of bidirectional diodes is provided between a first and second low-potential power supply nodes.Type: ApplicationFiled: April 9, 2008Publication date: October 16, 2008Applicant: SEIKO EPSON CORPORATIONInventors: Shinya Sato, Takayuki Saiki, Hiroyuki Takamiya, Masaaki Abe
-
Publication number: 20080224219Abstract: A semiconductor device is provided having a high performance resistance element. In an N-type well isolated by an insulating film, two higher concentration N-type regions are formed. An interlayer insulating film is also formed. In a plurality of openings in the interlayer insulating film, one electrode group having a plurality of electrodes is formed on one N-type region, while a second electrode group having a plurality of electrodes is formed on the other N-type region. The relationship between the two N-type regions is between an island region and an annular region surrounding the island. The annular region of the N-type well between the island region and the annular region serves as a resistor R. Thus, discharge channels for charges applied excessively because of ESD or the like evenly exist in the periphery (four regions) of the one N-type region.Type: ApplicationFiled: May 23, 2008Publication date: September 18, 2008Applicant: Seiko Epson CorporationInventors: Takayuki SAIKI, Kazuhiko Okawa
-
Patent number: 7394134Abstract: A semiconductor device is provided having a high performance resistance element. In an N-type well isolated by an insulating film, two higher concentration N-type regions are formed. An interlayer insulating film is also formed. In a plurality of openings in the interlayer insulating film, one electrode group having a plurality of electrodes is formed on one N-type region, while a second electrode group having a plurality of electrodes is formed on the other N-type region. The relationship between the two N-type regions is between an island region and an annular region surrounding the island. The annular region of the N-type well between the island region and the annular region serves as a resistor R. Thus, discharge channels for charges applied excessively because of ESD or the like evenly exist in the periphery (four regions) of the one N-type region.Type: GrantFiled: March 31, 2005Date of Patent: July 1, 2008Assignee: Seiko Epson CorporationInventors: Takayuki Saiki, Kazuhiko Okawa
-
Publication number: 20070187762Abstract: A semiconductor integrated circuit includes N pad rows in which pads are respectively arranged, and electrostatic discharge protection elements disposed in a lower layer of the N pad rows and connected with each pad in the N pad rows. The electrostatic discharge protection elements are disposed in a lower layer of regions at least partially including each of the N pads.Type: ApplicationFiled: February 8, 2007Publication date: August 16, 2007Applicant: SEIKO EPSON CORPORATIONInventors: Takayuki Saiki, Satoru Ito, Masahiko Moriguchi
-
Patent number: 7242061Abstract: The invention provides semiconductor devices having an output circuit in which transistors do not fail to achieve their original capability, and electrostatic breakdown is difficult to occur.Type: GrantFiled: January 14, 2003Date of Patent: July 10, 2007Assignee: Seiko Epson CorporationInventors: Kazuhiko Okawa, Takayuki Saiki
-
Publication number: 20070013634Abstract: An integrated circuit device includes at least one data driver block for driving data lines, a plurality of control transistors TC1 and TC2, each of the control transistors being provided corresponding to each output line of the data driver block and controlled. by using a common control signal, and a pad arrangement region in which data driver pads P1 and P2 for electrically connecting the data lines and the output lines QL1 and QL2 of the data driver block are disposed. The control transistors TC1 and TC2 are disposed in the pad arrangement region.Type: ApplicationFiled: June 30, 2006Publication date: January 18, 2007Applicant: SEIKO EPSON CORPORATIONInventors: Takayuki Saiki, Satoru Ito, Masahiko Moriguchi, Takashi Kumagai, Hisanobu Ishiyama, Takashi Fujise, Junichi Karasawa, Satoru Kodaira, Kazuhiro Maekawa
-
Publication number: 20070000971Abstract: An integrated circuit device includes first and second transistors NTr1 and PTr1 push-pull connected between first and second power supply lines and outputting a voltage of one of the first and second power supply lines to a connection node ND by a charge-pump operation, and a pad PD electrically connected with the connection node ND and electrically connected with a flying capacitor, to which a given voltage is applied at one end, at the other end of the flying capacitor. The pad PD is disposed in an upper layer of at least one of the first and second transistors NTr1 and PTr1 so that the pad PD overlaps part or the entirety of at least one of the first and second transistors NTr1 and PTr1.Type: ApplicationFiled: June 30, 2006Publication date: January 4, 2007Applicant: SEIKO EPSON CORPORATIONInventors: Takashi Kumagai, Hisanobu Ishiyama, Kazuhiro Maekawa, Satoru Ito, Takashi Fujise, Junichi Karasawa, Satoru Kodaira, Takayuki Saiki, Hiroyuki Takamiya
-
Publication number: 20070002509Abstract: An integrated circuit device includes a pad PDx and an electrostatic discharge protection element ESDx formed in a rectangular region and electrically connected with the pad PDx. The pad PDx is disposed in an upper layer of the electrostatic discharge protection element ESDx so that an arrangement direction of the pads is parallel to a long side direction of the region in which the electrostatic discharge protection element ESDx is formed, and the pad PDx overlaps part or the entirety of the electrostatic discharge protection element ESDx.Type: ApplicationFiled: June 30, 2006Publication date: January 4, 2007Applicant: Seiko Epson CorporationInventors: Takashi Kumagai, Hisanobu Ishiyama, Kazuhiro Maekawa, Satoru Ito, Takashi Fujise, Junichi Karasawa, Satoru Kodaira, Takayuki Saiki, Hiroyuki Takamiya