Patents by Inventor Takayuki Saiki

Takayuki Saiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050218454
    Abstract: A semiconductor device is provided having a high performance resistance element. In an N-type well isolated by an insulating film, two higher concentration N-type regions are formed. An interlayer insulating film is also formed. In a plurality of openings in the interlayer insulating film, one electrode group having a plurality of electrodes is formed on one N-type region, while a second electrode group having a plurality of electrodes is formed on the other N-type region. The relationship between the two N-type regions is between an island region and an annular region surrounding the island. The annular region of the N-type well between the island region and the annular region serves as a resistor R. Thus, discharge channels for charges applied excessively because of ESD or the like evenly exist in the periphery (four regions) of the one N-type region.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 6, 2005
    Inventors: Takayuki Saiki, Kazuhiko Okawa
  • Patent number: 6894351
    Abstract: The invention makes it possible to form thyristers and SCRs that show a good discharge efficiency upon application of static electricity in semiconductor devices using a SOI substrate. A semiconductor device is equipped with a connection terminal for connection with an external element, a dielectric substrate having a semiconductor layer formed therein, a first region of a first conductive type that is formed in the semiconductor layer and electrically connected to the connection terminal, a second region of a second conductive type that is formed in the semiconductor layer and electrically connected to the first region, a third region of the first conductive type that is formed adjacent to the second region in the semiconductor layer, and a fourth region of the second conductive type that is formed adjacent to the third region in the semiconductor layer.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: May 17, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Kazuhiko Okawa, Takayuki Saiki
  • Patent number: 6831334
    Abstract: A semiconductor device including an electrostatic protection circuit capable of preventing current from being concentrated in a hot spot through a silicide layer. A plurality of salicide N-type MOS transistors isolated by a first diffusion region are formed on a semiconductor substrate of this semiconductor device. An NPN lateral bipolar transistor and a Zener diode are formed as an electrostatic protection circuit for these MOS transistors. The NPN lateral bipolar transistor includes a P-type well and a second diffusion region which is formed in a region isolated by two second isolation regions. The Zener diode is formed by the PN junction between the first diffusion region of the MOS transistor and a third diffusion region. The breakdown start voltage of the Zener diode is set to be lower than the breakdown start voltage of the MOS transistor.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: December 14, 2004
    Assignee: Seiko Epson Corporation
    Inventors: Kazuhiko Okawa, Takayuki Saiki
  • Publication number: 20030151096
    Abstract: The invention provides semiconductor devices having an output circuit in which transistors do not fail to achieve their original capability, and electrostatic breakdown is difficult to occur.
    Type: Application
    Filed: January 14, 2003
    Publication date: August 14, 2003
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kazuhiko Okawa, Takayuki Saiki
  • Publication number: 20030141545
    Abstract: The invention makes it possible to form thyristers and SCRs that show a good discharge efficiency upon application of static electricity in semiconductor devices using a SOI substrate. A semiconductor device is equipped with a connection terminal for connection with an external element, a dielectric substrate having a semiconductor layer formed therein, a first region of a first conductive type that is formed in the semiconductor layer and electrically connected to the connection terminal, a second region of a second conductive type that is formed in the semiconductor layer and electrically connected to the first region, a third region of the first conductive type that is formed adjacent to the second region in the semiconductor layer, and a fourth region of the second conductive type that is formed adjacent to the third region in the semiconductor layer.
    Type: Application
    Filed: December 27, 2002
    Publication date: July 31, 2003
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kazuhiko Okawa, Takayuki Saiki
  • Patent number: 6455897
    Abstract: A semiconductor device, including an electrostatic discharge protection circuit capable of preventing current from being concentrated in a hot spot through a silicide layer, includes an N-type MOS transistor having a first diffusion region on a semiconductor substrate. This N-type MOS transistor is isolated from another MOS transistor by a first element isolation region. A second diffusion region is formed between the first diffusion region and first element isolation region. The first and second diffusion regions are separated by a second element isolation region. A silicide is formed on the surface of the semiconductor substrate excluding the first and second element isolation regions. A pad is connected to the second N-type diffusion region through a contact.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: September 24, 2002
    Assignee: Seiko Epson Corporation
    Inventors: Kazuhiko Okawa, Takayuki Saiki
  • Publication number: 20020030231
    Abstract: A semiconductor device including an electrostatic protection circuit capable of preventing current from being concentrated in a hot spot through a silicide layer. A plurality of salicide N-type MOS transistors isolated by a first diffusion region are formed on a semiconductor substrate of this semiconductor device. An NPN lateral bipolar transistor and a Zener diode are formed as an electrostatic protection circuit for these MOS transistors. The NPN lateral bipolar transistor includes a P-type well and a second diffusion region which is formed in a region isolated by two second isolation regions. The Zener diode is formed by the PN junction between the first diffusion region of the MOS transistor and a third diffusion region. The breakdown start voltage of the Zener diode is set to be lower than the breakdown start voltage of the MOS transistor.
    Type: Application
    Filed: May 30, 2001
    Publication date: March 14, 2002
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kazuhiko Okawa, Takayuki Saiki
  • Publication number: 20020030230
    Abstract: A semiconductor device including an electrostatic discharge protection circuit capable of preventing current from being concentrated in a hot spot through a silicide layer includes an N-type MOS transistor having a first diffusion region on a semiconductor substrate. This N-type MOS transistor is isolated from another MOS transistor by a first element isolation region. A second diffusion region is formed between the first diffusion region and first element isolation region. The first and second diffusion regions are separated by a second element isolation region. A silicide is formed on the surface of the semiconductor substrate excluding the first and second element isolation regions. A pad is connected to the second N-type diffusion region through a contact.
    Type: Application
    Filed: May 30, 2001
    Publication date: March 14, 2002
    Applicant: Seiko Epson Corporation
    Inventors: Kazuhiko Okawa, Takayuki Saiki