Patents by Inventor Takayuki Sakai
Takayuki Sakai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160137639Abstract: A compound represented by Formula [I]: or pharmaceutically acceptable salt thereof, wherein each symbol is as defined in the description.Type: ApplicationFiled: October 25, 2013Publication date: May 19, 2016Inventors: Masayuki KOTOKU, Takaki MAEBA, Noriyoshi SEKI, Shintaro HIRASHIMA, Shingo FUJIOKA, Shingo OBIKA, Hiroshi YAMANAKA, Masahiro YOKOTA, Takayuki SAKAI, Kazuyuki HIRATA, Katsuya MAEDA, Makoto SHIOZAKI, Yuko SHINAGAWA, Taku IKENOGAMI, Satoki DOI, Takahiro OKA, Takuya MATSUO, Yoshihiro SUWA, Keisuke ITO, Satoru NOJI, Yoshinori HARA
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Publication number: 20150262879Abstract: According to one embodiment, the plasma dicing method includes a deposition process depositing a film on the dicing region and on the metal electrodes exposed to the pad opening in an atmosphere containing a plasma of a first gas. The plasma dicing method includes an etching process etching the film by applying a first bias power to a lower electrode supporting the wafer in an atmosphere containing a plasma of a second gas. The substrate is etched by reducing the first bias power to a second bias power when light emission due to etching of the substrate at the dicing region is detected during the etching process.Type: ApplicationFiled: September 9, 2014Publication date: September 17, 2015Inventor: Takayuki Sakai
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Patent number: 8994445Abstract: A CPU outputs a high level ENB signal to a USB-IC via an ENB line and monitors, after outputting the ENB signal, whether or not there is an overcurrent in the USB-IC on the basis of the voltage level of the ENB line. The USB-IC outputs, when it receives the ENB signal, a 5 V voltage to a VBUS line and stops, when an overcurrent occurs, output of the 5 V voltage to the VBUS line. A connector changes the voltage level of the ENB line to a high voltage level using the 5 V voltage of the VBUS line and changes, when output of the 5 V voltage is stopped, the voltage level of the ENB line to a low level. Thus, the ENB line may be shared for outputting the ENB signal from the CPU and for providing notification of an overcurrent from the USB-IC.Type: GrantFiled: March 14, 2013Date of Patent: March 31, 2015Assignee: Seiko Epson CorporationInventor: Takayuki Sakai
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Publication number: 20140296306Abstract: A compound of formula [I-W]: wherein each symbol is as defined in the description, or a pharmaceutically acceptable salt thereof.Type: ApplicationFiled: October 30, 2013Publication date: October 2, 2014Applicant: Japan Tobacco Inc.Inventors: Takaki Maeba, Katsuya Maeda, Masayuki Kotoku, Kazuyuki Hirata, Noriyoshi Seki, Hiroshi Yamanaka, Takayuki Sakai, Shintaro Hirashima, Shingo Obika, Makoto Shiozaki, Masahiro Yokota
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Patent number: 8716782Abstract: In general, according to one embodiment, a power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a trench, a gate insulating film, and a gate electrode. The second semiconductor layer is provided on the first semiconductor layer. The trench is provided from the second semiconductor layer to the first semiconductor layer. The gate insulating film is composed of an oxide film and a protective layer formed on the oxide film. The protective layer is opposed to the second semiconductor layer across the oxide film in the trench. The oxide film covers the second semiconductor layer exposed at a sidewall of the trench and includes at least one of aluminum and yttrium. The gate electrode is made of n-type polysilicon buried in the trench in direct contact with the gate insulating film.Type: GrantFiled: September 12, 2011Date of Patent: May 6, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Takayuki Sakai
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Patent number: 8716137Abstract: According to an embodiment, a method for etching polycrystalline silicon includes a step of holding the polycrystalline silicon at a temperature higher than or equal to TE (K) given in a following equation; and a step of etching the polycrystalline silicon by dry etching with an etching gas containing CF4 and O2, T E = - 0.114 ? x + 0.0556 k × ln ? { ( 1 - r / d ) × - 6.27 ? x + 5.38 - 2.01 ? x + 3.11 } where d (nm) is etching amount of the polycrystalline silicon, r (nm) is surface roughness of the polycrystalline silicon after the etching, x is ratio of flow rate of CF4 gas to sum of flow rate of the CF4 gas and flow rate of O2 gas, and k (eV/K) is Boltzmann constant.Type: GrantFiled: August 30, 2012Date of Patent: May 6, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Takayuki Sakai
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Publication number: 20140070309Abstract: A semiconductor device is provided with a semiconductor substrate including a drain layer of a first conductivity type, a base layer of a second conductivity type, and a source layer of the first conductivity type, a gate insulating film, a gate electrode, an insulating section, a source electrode, and a drain electrode. Gate trenches are formed on an upper surface of the semiconductor substrate. A curved section is formed on the upper surface of the semiconductor substrate between the gate trenches in the semiconductor substrate. The base layer is disposed between the gate trenches, and the source layer is formed above the base layer at both ends of the curved section.Type: ApplicationFiled: March 4, 2013Publication date: March 13, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Takayuki Sakai
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Publication number: 20140065829Abstract: According to one embodiment, a trench formation method uses a plasma source to make a trench in a silicon substrate by alternately repeating a depositing step and an etching step. The method includes implementing the depositing step and the etching step to satisfy the formulas recited below, where a distance between the silicon substrate and a region where plasma is to be confined is x (mm), an RF power to induce the plasma is w (kW), a pressure of the depositing step is y (Pa), and a tolerable limit of fluctuation in a plane of the silicon substrate of a width of the trench to be made is z0 (?m). 2.8w2+0.018y2?0.42wy?12w+0.91y+14?z0 ?0.010x+0.039y+0.37?z0 0.00066x2+0.0064y2+0.52w2?0.018xy+0.037xw+0.0044yw?0.12x?0.048y?3.7w+6.Type: ApplicationFiled: March 18, 2013Publication date: March 6, 2014Inventors: Takayuki SAKAI, Noriaki KATAGIRI
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Patent number: 8604069Abstract: A compound of formula [I-W]: wherein each symbol is as defined in the description, or a pharmaceutically acceptable salt thereof.Type: GrantFiled: April 27, 2012Date of Patent: December 10, 2013Assignee: Japan Tobacco Inc.Inventors: Takaki Maeba, Katsuya Maeda, Masayuki Kotoku, Kazayuki Hirata, Noriyoshi Seki, Hiroshi Yamanaka, Takayuki Sakai, Shintaro Hirashima, Shingo Obika, Makoto Shiozaki, Masahiro Yokota
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Publication number: 20130271206Abstract: A CPU outputs a high level ENB signal to a USB-IC via an ENB line and monitors, after outputting the ENB signal, whether or not there is an overcurrent in the USB-IC on the basis of the voltage level of the ENB line. The USB-IC outputs, when it receives the ENB signal, a 5 V voltage to a VBUS line and stops, when an overcurrent occurs, output of the 5 V voltage to the VBUS line. A connector changes the voltage level of the ENB line to a high voltage level using the 5 V voltage of the VBUS line and changes, when output of the 5 V voltage is stopped, the voltage level of the ENB line to a low level. Thus, the ENB line may be shared for outputting the ENB signal from the CPU and for providing notification of an overcurrent from the USB-IC.Type: ApplicationFiled: March 14, 2013Publication date: October 17, 2013Applicant: SEIKO EPSON CORPORATIONInventor: Takayuki Sakai
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Publication number: 20130221431Abstract: A method for manufacturing a semiconductor device includes forming a first insulating film on inner surfaces of trenches arranged in parallel in a semiconductor layer, forming a control electrode on the first insulating film, and forming a second insulating film on the control electrode, where the upper surface of the second insulating film is lower than the upper end of the first insulating film. In addition, the method includes etching the semiconductor layer to a depth near the upper end of the control electrode and forming a first semiconductor region. The method further includes forming a conductive film and then a second semiconductor region in the upper portion of the first semiconductor region by diffusion of impurities from the conductive film into the upper portion of the first semiconductor region, and forming a contact hole by etching back the conductive layer.Type: ApplicationFiled: September 6, 2012Publication date: August 29, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yuta MUSHA, Takayuki SAKAI, Hideki OKUMURA, Takahiro KAWANO
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Publication number: 20130210204Abstract: According to an embodiment, a method for etching polycrystalline silicon includes a step of holding the polycrystalline silicon at a temperature higher than or equal to TE (K) given in a following equation; and a step of etching the polycrystalline silicon by dry etching with an etching gas containing CF4 and O2, T E = - 0.114 ? x + 0.0556 k × ln ? { ( 1 - r / d ) × - 6.27 ? x + 5.38 - 2.01 ? x + 3.11 } where d (nm) is etching amount of the polycrystalline silicon, r (nm) is surface roughness of the polycrystalline silicon after the etching, x is ratio of flow rate of CF4 gas to sum of flow rate of the CF4 gas and flow rate of O2 gas, and k (eV/K) is Boltzmann constant.Type: ApplicationFiled: August 30, 2012Publication date: August 15, 2013Applicant: Kabushiki Kaisha ToshibaInventor: Takayuki SAKAI
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Patent number: 8339615Abstract: An edge detection method includes preparing a transparent substrate which includes a first main face having a first main region and a first peripheral region and a second main face having a second main region and a second peripheral region, the first peripheral region having an inclination angle of ?a1 and the second peripheral region having an inclination angle of ?a2, causing measuring light to enter the first peripheral region from a direction perpendicular to the first main region, detecting a non-emitting region where the measuring light is not emitted from the second peripheral region, and detecting an edge of the transparent substrate on the basis of the non-emitting region, wherein if a refractive index of the transparent substrate is n, the inclination angles ?a1 and ?a2satisfy the following expression: n×sin(?a1+?a2?arcsin(sin ?a1/n))?1.Type: GrantFiled: July 28, 2009Date of Patent: December 25, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Dohi, Itsuko Sakai, Takayuki Sakai, Shunji Kikuchi, Takuto Inoue, Akihiro Hori, Masayuki Narita
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Publication number: 20120322837Abstract: A compound of formula [I-W]: wherein each symbol is as defined in the description, or a pharmaceutically acceptable salt thereof.Type: ApplicationFiled: April 27, 2012Publication date: December 20, 2012Applicant: JAPAN TOBACCO INC.Inventors: Takaki Maeba, Katsuya Maeda, Masayuki Kotoku, Kazuyuki Hirata, Noriyoshi Seki, Hiroshi Yamanaka, Takayuki Sakai, Shintaro Hirashima, Shingo Obika, Makoto Shiozaki, Masahiro Yokota
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Publication number: 20120061749Abstract: In general, according to one embodiment, a power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a trench, a gate insulating film, and a gate electrode. The second semiconductor layer is provided on the first semiconductor layer. The trench is provided from the second semiconductor layer to the first semiconductor layer. The gate insulating film is composed of an oxide film and a protective layer formed on the oxide film. The protective layer is opposed to the second semiconductor layer across the oxide film in the trench. The oxide film covers the second semiconductor layer exposed at a sidewall of the trench and includes at least one of aluminum and yttrium. The gate electrode is made of n-type polysilicon buried in the trench in direct contact with the gate insulating film.Type: ApplicationFiled: September 12, 2011Publication date: March 15, 2012Applicant: Kabushiki Kaisha ToshibaInventor: Takayuki SAKAI
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Publication number: 20110304054Abstract: According to one embodiment, a semiconductor device including a conductive layer formed in a trench formed in a semiconductor substrate via an insulating film, an opening portion of the trench being formed with a plurality of interconnected concaves and with a curved surface as a folding fan so as to set to be the opening portion gradually wider from a sidewall of the trench towards a surface of the semiconductor substrate.Type: ApplicationFiled: March 18, 2011Publication date: December 15, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Takayuki Sakai
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Patent number: 7994447Abstract: Upward urging force by operation force of a tact switch and restoring force of a rubber body are applied to an operation body via a pressing body. Then, pressing operation of a push button section causes the operation body to press down the rear ends of left and right sections of the pressing body. This follows that, with both contact sections in contact with a step section functioning as the support points, an operation section on the front end of the pressing body is pressed up to turn on the tact switch. In this process, when the push button section is pressed, the center of rotation of the operation body is changed depending on which portion of the push button section is pressed, causing the distance between a pressed portion of the operation body and the center of the rotation are almost equal independent of which portion is pressed. As a result, the load to operate the push button section is substantially equalized independent of which portion of the operation body is pressed.Type: GrantFiled: August 21, 2007Date of Patent: August 9, 2011Assignee: Idec CorporationInventor: Takayuki Sakai
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Patent number: 7960665Abstract: Provided is a pushbutton switch device provided with a switch case in which a depressing member is arranged which, when moved downwards, depresses a switch. Arranged inside the switch case is an operating member which, when depressed, comes into contact with the depressing member to move the depressing member downwards. Provided in the peripheral edge of the operating member are a plurality of engagement portions to be engaged with the peripheral edge of the switch case. When the operating member is depressed, the depressed portion of the operating member rotates downwardly using, as a fulcrum, the engagement portion corresponding to the depressed portion of the operating member.Type: GrantFiled: February 2, 2006Date of Patent: June 14, 2011Assignees: IDEC Corporation, Mitsubishi Electric CorporationInventors: Takayuki Sakai, Eiji Yuasa
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Publication number: 20100224471Abstract: Upward urging force by operation force of a tact switch and restoring force of a rubber body are applied to an operation body via a pressing body. Then, pressing operation of a push button section causes the operation body to press down the rear ends of left and right sections of the pressing body. This follows that, with both contact sections in contact with a step section functioning as the support points, an operation section on the front end of the pressing body is pressed up to turn on the tact switch. In this process, when the push button section is pressed, the center of rotation of the operation body is changed depending on which portion of the push button section is pressed, causing the distance between a pressed portion of the operation body and the center of the rotation are almost equal independent of which portion is pressed. As a result, the load to operate the push button section is substantially equalized independent of which portion of the operation body is pressed.Type: ApplicationFiled: August 21, 2007Publication date: September 9, 2010Inventor: Takayuki Sakai
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Patent number: 7685855Abstract: A vertically oscillating working device 2 has a body to be oscillated 23 having an inner space that is formed by a cover member 21 and a vehicle wheel 22, which is a body to be worked, and receives working materials 25 in it and also has oscillating means for vertically oscillating the body to be oscillated 23. The working materials 25 are allowed to collide with the vehicle wheel 22 by the oscillation, and thereby the vehicle wheel 22 is worked. With the working device 2, a casting can be oscillated together with hardening materials, and excellent mechanical properties can be uniformly added to a predetermined portion of the casting by the oscillation without changing the position of the casting.Type: GrantFiled: March 30, 2007Date of Patent: March 30, 2010Assignee: Asahi Tec CorporationInventors: Matsuo Suzuki, Shinichirou Azuma, Takayuki Sakai, Kiyomi Hagita, Atsurou Yamamoto