Abstract: A multi-lane re-timer circuit includes: a clock generation circuit to generate a base clock; and reception circuits to generate a reception clock and receive input data signals from lanes, wherein each of the reception circuits includes: a phase frequency detector to generate phase difference signal and frequency difference signal between the input data signal and the reception clock; a clock data regeneration controller to generate a control signal based on the phase difference signal; a phase rotator to generate the reception clock from the base clock; and a decision circuit to receive the input data signal, and wherein the clock generation circuit includes: an input selector to select a signal; a charge pump to generate a charge signal; a loop filter to remove a high frequency component from the charge signal to output a voltage control signal; and a voltage controlled oscillator to generate the reception clock.

Abstract: A clock data recovery circuit includes: a phase detector circuit configured to generate a phase detection signal indicating a first detection result between a phase of a reception data signal and a phase of a first clock signal; a clock signal generation circuit configured to generate the first clock signal and a second clock signal based on the phase detection signal, the second clock signal having a frequency substantially equal to a frequency of the first clock signal, a phase difference between the first clock signal and the second clock signal being less than 180°; a phase combining circuit configured to combine the first clock signal and the second clock signal in accordance with a phase relation and generate a recovered clock signal; and a recovered data generation circuit configured to sample the reception data signal and generate a recovered data signal based on the recovered clock signal.

Abstract: A reception circuit includes: an equalizer; a comparator to compare an output signal of the equalizer with first, second, and third thresholds at a first-timing to output first, second, and third comparison-results, respectively; a selector to select any one of the first and second comparison-results based on a determination-result at a timing before the first-timing, and update the determination-result; a detector to detect a phase information based on the first or second comparison-result not selected; a shifter to adjust a sampling clock phase based on the phase information detected; and a controller to set a third threshold based on the first and second thresholds by either adjusting the first and second thresholds based on the output signal amplitude or adding/subtracting a first value to/from the output signal, detect an equalization-result based on the third comparison-result by the set third threshold, and adjust an equalization coefficient based on the detected equalization-result.

Abstract: In a receiver circuit which can correct a deviation of phase between an input signal and a clock, a sampler detects an amplitude level of the input signal at timing indicated by the clock, a first comparison circuit compares a first and a second amplitude level detected by the sampler at first and second timings, respectively, with a determined threshold, an interpolation circuit calculates an intermediate level that approximates to an amplitude level of the input signal corresponding to an intermediate point between the first and second timings by an interpolation process based on the first and second amplitude levels, a second comparison circuit compares the intermediate level with the determined threshold, and a phase deviation detection circuit detects the deviation of phase between the clock and the input signal on the basis of comparison results obtained by the first and second comparison circuits.

Abstract: A decision feedback equalizer includes: L equalization calculation circuits to perform an equalization calculation of a first sample of input data for each of M combinations of data decision values of a second sample sampled from the input data before sampling the first sample; a first logic circuit to generate first M logical values by selecting and arranging calculation values of M calculation values calculated by at least one equalization calculation circuit among the L equalization calculation circuits based on a data decision value for a third sample sampled before sampling the first data; and a selection circuit to select one of the first M logical values based on a data decision value for a fourth sample sampled before sampling the third sample, and to output the selected logical value as a data decision value of the first sample.

Abstract: An interpolation circuit includes: a generation circuit configured to generate interpolated data based on a plurality of pieces of input data in time sequence; a first analog digital converter configured to convert first interpolated data at a data point of the interpolated data into first digital data; and a second analog digital converter configured to convert second interpolated data at a change point into second digital data of the interpolated data, a second number of quantization bits of the second analog digital converter being smaller than a first number of quantization bits of the first analog digital converter.

Abstract: A burst mode CDR detects an edge from a data signal superimposed with a clock, and generates a recovered clock by means of a voltage controlled oscillator whose oscillation operation is reset based on a timing when the edge is detected. A phase adjustment unit adjusts the phase of a data signal so as to coincide with the phase of a recovered clock. A PLL-based CDR adjusts the oscillation frequency of the recovered clock by means of the voltage controlled oscillator, based on a phase difference between a data signal whose phase has been adjusted by the phase adjustment unit and a feedback clock from the voltage controlled oscillator. A determination unit determines the value of the data signal at a timing when the signal level of the recovered clock transitions.

Abstract: In a receiver circuit which can correct a deviation of phase between an input signal and a clock, a sampler detects an amplitude level of the input signal at timing indicated by the clock, a first comparison circuit compares a first and a second amplitude level detected by the sampler at first and second timings, respectively, with a determined threshold, an interpolation circuit calculates an intermediate level that approximates to an amplitude level of the input signal corresponding to an intermediate point between the first and second timings by an interpolation process based on the first and second amplitude levels, a second comparison circuit compares the intermediate level with the determined threshold, and a phase deviation detection circuit detects the deviation of phase between the clock and the input signal on the basis of comparison results obtained by the first and second comparison circuits.

Abstract: A receiving circuit includes: a sampling circuit to sample input data in synchronization with first clock to obtain boundary data, and sample the input data in synchronization with second clock to obtain center data; a decision feedback equalizer to perform equalization on the center data using an equalization coefficient, and output first output data; a first comparator circuit to perform binary decision on the boundary data and output second output data; a phase detection circuit to detect phase information of the input data using the first output data and the second output data; a phase difference computation circuit to calculate phase difference of the first output data using the equalization coefficient; a first phase adjustment circuit to adjust phase of the first clock using the phase information; and a second phase adjustment circuit to adjust phase of the second clock using the phase information and the phase difference.

Abstract: An apparatus includes an integration circuit that integrates values of one of a data center and a data edge of input data, based on clock signals, a sampling circuit that samples another at the data center and a data edge of the input data, based on clock signals, a first determination circuit that determines a data value of an integration value of the integration circuit, a second determination circuit that determines a data value of a sampling value of the sampling circuit, a phase detection circuit that detects phase information of the input data, based on a data value determined by the first determination circuit and the second determination circuit, and a phase adjusting circuit that adjusts a phase of a reference clock so as to track a phase of the input data, in accordance with the phase information, so as to output as the clock signals.

Abstract: An interpolation circuit includes: a generation circuit configured to generate interpolated data based on a plurality of pieces of input data in time sequence; a first analog digital converter configured to convert first interpolated data at a data point of the interpolated data into first digital data; and a second analog digital converter configured to convert second interpolated data at a change point into second digital data of the interpolated data, a second number of quantization bits of the second analog digital converter being smaller than a first number of quantization bits of the first analog digital converter.

Abstract: A reception circuit includes: a sampling circuit to sample an input data signal based on a clock signal and output a sampled signal; a data interpolation circuit to interpolate the sampled signal based on phase information corresponding to the sampled signal and output an interpolated data signal; an interpolation error decision circuit to output an interpolation error based on the sampled signal and the phase information; a decision/equalization circuit to equalize the interpolated data signal using an equalization coefficient set based on the interpolation error, to check an equalized interpolated data signal and to output a checked signal; and a phase detection circuit to generate the phase information based on at least one of the checked signal and the equalized interpolated data signal and output the phase information to the data interpolation circuit and the interpolation error decision circuit.

Abstract: An apparatus includes an integration circuit that integrates values of one of a data center and a data edge of input data, based on clock signals, a sampling circuit that samples another at the data center and a data edge of the input data, based on clock signals, a first determination circuit that determines a data value of an integration value of the integration circuit, a second determination circuit that determines a data value of a sampling value of the sampling circuit, a phase detection circuit that detects phase information of the input data, based on a data value determined by the first determination circuit and the second determination circuit, and a phase adjusting circuit that adjusts a phase of a reference clock so as to track a phase of the input data, in accordance with the phase information, so as to output as the clock signals.

Abstract: A receiving circuit includes: a clock generating circuit to generate a plurality of clock signals in a cycle; an oversampling circuit to oversample input data based on the plurality of clock signals and output a plurality of samples of digital data in a unit interval; a data boundary determining circuit to detect a changing point of the digital data, determine data boundaries of the unit interval based on the changing point, and output digital data corresponding to a central data between the data boundaries; and a clock phase control circuit to control a phase of at least one of the plurality of clock signals so that a first number of the plurality of samples becomes a certain value when a second number of samples between the data boundaries is larger than a threshold value.

Abstract: A clock signal distributing device includes a plurality of LC resonant oscillators, each resonating at a frequency conforming to values of a first inductor and a first capacitor to oscillate a signal, an injection locked LC resonant oscillator that resonates at a frequency conforming to values of a second inductor and a second capacitor to oscillate a signal which is synchronous with an input clock signal, and transmission lines that connect oscillation nodes of the plurality of LC resonant oscillators and the injection locked LC resonant oscillator with one another.

Abstract: A reception circuit includes: a sampling circuit to sample an input data signal based on a clock signal and output a sampled signal; a data interpolation circuit to interpolate the sampled signal based on phase information corresponding to the sampled signal and output an interpolated data signal; an interpolation error decision circuit to output an interpolation error based on the sampled signal and the phase information; a decision/equalization circuit to equalize the interpolated data signal using an equalization coefficient set based on the interpolation error, to check an equalized interpolated data signal and to output a checked signal; and a phase detection circuit to generate the phase information based on at least one of the checked signal and the equalized interpolated data signal and output the phase information to the data interpolation circuit and the interpolation error decision circuit.

Abstract: A decision feedback equalizer includes: L equalization calculation circuits to perform an equalization calculation of a first sample of input data for each of M combinations of data decision values of a second sample sampled from the input data before sampling the first sample; a first logic circuit to generate first M logical values by selecting and arranging calculation values of M calculation values calculated by at least one equalization calculation circuit among the L equalization calculation circuits based on a data decision value for a third sample sampled before sampling the first data; and a selection circuit to select one of the first M logical values based on a data decision value for a fourth sample sampled before sampling the third sample, and to output the selected logical value as a data decision value of the first sample.

Abstract: A receiving circuit includes: a clock generating circuit to generate a plurality of clock signals in a cycle; an oversampling circuit to oversample input data based on the plurality of clock signals and output a plurality of samples of digital data in a unit interval; a data boundary determining circuit to detect a changing point of the digital data, determine data boundaries of the unit interval based on the changing point, and output digital data corresponding to a central data between the data boundaries; and a clock phase control circuit to control a phase of at least one of the plurality of clock signals so that a first number of the plurality of samples becomes a certain value when a second number of samples between the data boundaries is larger than a threshold value.

Abstract: A clock signal distributing device includes a plurality of LC resonant oscillators, each resonating at a frequency conforming to values of a first inductor and a first capacitor to oscillate a signal, an injection locked LC resonant oscillator that resonates at a frequency conforming to values of a second inductor and a second capacitor to oscillate a signal which is synchronous with an input clock signal, and transmission lines that connect oscillation nodes of the plurality of LC resonant oscillators and the injection locked LC resonant oscillator with one another.