Patents by Inventor Takayuki Tamura

Takayuki Tamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6557088
    Abstract: An information processing system which has a disk buffer for temporarily storing data items read from a disk unit, a block processing order determination module for detecting, from a processing request for requesting data items stored on the disk unit, a data item matching the data stored in the disk buffer from the data items requested in the processing request and determining the read order of the data item matching and the remaining data requested in the processing request so that the data item matching is read before the remaining data, and a read module for reading the data item matching from the disk buffer before reading the remaining data into the disk buffer from the disk unit in accordance with the read order determined by the block processing order determination module.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: April 29, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takayuki Tamura
  • Publication number: 20030072203
    Abstract: A semiconductor memory includes a memory block consisting of a plurality of cells, a write control section, and a read control section. The write control section sets a potential to each of the plurality of cells in such a manner that the potential corresponds to a level indicated by a bit data string obtained by arranging pieces of bit data which are stored in buffers A and B and which are to be stored in the cell in the order of the buffer A and the buffer B. The read control section has a discriminator corresponding to each of the plurality of cells. The discriminator sets a threshold voltage to a potential level that corresponds to a number of discriminating operations to be performed with respect to a corresponding cell and a result of a discriminating operation already performed with respect to the cell.
    Type: Application
    Filed: November 26, 2002
    Publication date: April 17, 2003
    Inventors: Kunihiro Katayama, Takayuki Tamura, Kiyoshi Inoue
  • Patent number: 6542405
    Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: April 1, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
  • Patent number: 6535422
    Abstract: The present invention provides a nonvolatile memory system whose storage capacity can be easily changed. The nonvolatile memory system comprises plural memory modules, a controller for controlling the operation of the plural memory modules according to access requests from the outside, and a module selecting decoder for selectively enabling the memory modules by decoding a selection signal outputted from the controller, wherein the memory modules are freely mounted or dismounted. With this arrangement, the storage capacity can be changed by increasing or decreasing the memory modules.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: March 18, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroyuki Goto, Shigemasa Shiota, Takayuki Tamura, Hirofumi Shibuya, Yasuhiro Nakamura
  • Publication number: 20030048659
    Abstract: In a card storage device containing a non-volatile memory and a buffer memory, the buffer memory includes a plurality of banks. Data is transferred sequentially from a host CPU to the banks of the buffer memory, data is transferred to the non-volatile memory from a bank that becomes full, a write operation is started when one unit of data to be written into the non-volatile memory at a time has been transferred and, without waiting for the data to be written, the next write data is transferred from the host CPU to a bank from which write data has been transferred.
    Type: Application
    Filed: February 26, 2002
    Publication date: March 13, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Motoki Kanamori, Takayuki Tamura, Kenji Kozakai, Atsushi Shikata, Shinsuke Asari
  • Publication number: 20030033567
    Abstract: A memory card includes a non-volatile memory, a memory controller for controlling the operation of the memory card. The memory controller is capable of providing an interface with outside according to a predetermined protocol, and performs error detection and correction of the memory information at regular time intervals or at the timing of connection of electric power supply, independently of reading out the memory information according to external access request. Therefore, it is possible to improve reliability of data retention in the non-volatile memory without the host device reading out the memory information from the non-volatile memory of the memory card.
    Type: Application
    Filed: February 26, 2002
    Publication date: February 13, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Takayuki Tamura, Hirofumi Shibuya, Hiroyuki Goto, Shigemasa Shiota, Yasuhiro Nakamura
  • Publication number: 20030033573
    Abstract: A memory card has a plurality of non-volatile memories and a main controller for controlling the operation of the non-volatile memories. The main controller performs an access control to the non-volatile memories in response to an external access instruction, and an alternate control for alternating an access error-related storage area of the non-volatile memory with other storage area. In the access control, the speeding up of the data transfer between flash memories is achieved by causing the plurality of non-volatile memories to parallel access operate. In the alternation control, the storage areas is made alternative for each non-volatile memory in which an access error occurs.
    Type: Application
    Filed: February 27, 2002
    Publication date: February 13, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Takayuki Tamura, Hirofumi Shibuya, Hiroyuki Goto, Shigemasa Shiota
  • Publication number: 20030021151
    Abstract: In the conventional nonvolatile memory, it is not possible to determine the cause of the error is accidental or due to the degradation when the error is detect at the time of data read. Therefore, unnecessary substitute processing is performed, resulting in the exhaustion of the substitute area to shorten the life of the storage device.
    Type: Application
    Filed: September 19, 2002
    Publication date: January 30, 2003
    Inventors: Kunihiro Katayama, Takayuki Tamura, Yusuke Jono, Motoki Kanamori, Atsushi Shikata
  • Patent number: 6493273
    Abstract: A semiconductor memory includes a memory block consisting of a plurality of cells, a write control section, and a read control section. The write control section sets a potential to each of the plurality of cells in such a manner that the potential corresponds to a level indicated by a bit data string obtained by arranging pieces of bit data which are stored in buffers A and B and which are to be stored in the cell in the order of the buffer A and the buffer B. The read control section has a discriminator corresponding to each of the plurality of cells. The discriminator sets a threshold voltage to a potential level that corresponds to a number of discriminating operations to be performed with respect to a corresponding cell and a result of a discriminating operation already performed with respect to the cell.
    Type: Grant
    Filed: September 4, 2001
    Date of Patent: December 10, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Kunihiro Katayama, Takayuki Tamura, Kiyoshi Inoue
  • Publication number: 20020178338
    Abstract: This invention realizes separate control for each memory area. A memory unit is structured by including a semiconductor memory device capable of memorizing information, the aforementioned memory device is divided into plural memory areas logically and also management table, which is capable of controlling separately each aforementioned memory area for accessing from the outside, is tabled, control information, which prohibits accessing the prescribed memory area of the aforementioned plural memory areas, is provided in the aforementioned management information, and it is prohibited to access the specified memory area from the outside in accordance with control information.
    Type: Application
    Filed: February 25, 2002
    Publication date: November 28, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Hirofumi Shibuya, Takayuki Tamura, Hiroyuki Goto, Shigemasa Shiota, Yasuhiro Nakamura
  • Publication number: 20020174294
    Abstract: An information processing system which has a disk buffer 53 for temporarily storing a plurality of data pieces read from a disk unit 6, a block processing order determination module 55 for detecting from a processing request for requesting a plurality of data pieces stored on the disk unit 6, the data piece matching the data stored in the disk buffer 53 among the data pieces requested in the processing request and determining the read order of the match data piece and the remaining data requested in the processing request so as to read the match data piece preceding the remaining data, and read means for reading the match data piece from the disk buffer 53 before reading the remaining data into the disk buffer 53 from the disk unit 6 in accordance with the read order determined by the block processing order determination module 55.
    Type: Application
    Filed: July 17, 2002
    Publication date: November 21, 2002
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Takayuki Tamura
  • Patent number: 6480416
    Abstract: A semiconductor storage device that determines the cause of an error at the time of the error correction of data read out from a non-volatile semiconductor memory, on the basis of a previously recorded error correction count, and selects a data refresh processing or a substitute processing to perform. When the error is detected, the corrected data is rewritten back for preventing reoccurrence of error due to accidental cause. If it is determined that the reoccurrence frequency of the error is high and the error is due to degradation of the storage medium, based on the error correction count, the substitute processing is performed.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: November 12, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Kunihiro Katayama, Takayuki Tamura, Yusuke Jono, Motoki Kanamori, Atsushi Shikata
  • Patent number: 6459644
    Abstract: In the present invention, disclosed is a semiconductor memory device capable of reducing the number of erasing times of each block allocated to a cluster or the number of blocks to be erased in one writing to the minimum. As an embodiment of the present invention, when a host system 1 performs accessing, for each cluster as a unit, to the FAT partition prepared on a flash memory 17 of the semiconductor memory device 100, a CPU 6 adds an address offset value held by address offset storage section 10 to a logical address specified by the host system 1, whereby a logical address of a head sector of the cluster correspond to a physical address of a head sector of a unit block for erasing/writing data in the flash memory 17.
    Type: Grant
    Filed: February 9, 2001
    Date of Patent: October 1, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Nagamasa Mizushima, Kunihiro Katayama, Kazunori Furusawa, Tomihisa Hatano, Takayuki Tamura
  • Patent number: 6457097
    Abstract: An information processing system which has a disk buffer for temporarily storing data items read from a disk unit, a block processing order determination module for detecting, from a processing request for requesting data items stored on the disk unit, a data item matching the data stored in the disk buffer and determining the read order of the data item matching and the remaining data requested in the processing request so that the data item matching is read before the remaining data, and a read module for reading the data item matching from the disk buffer before reading the remaining data into the disk buffer from the disk unit in accordance with the read order determined by the block processing order determination module.
    Type: Grant
    Filed: September 28, 1999
    Date of Patent: September 24, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Takayuki Tamura
  • Publication number: 20020097604
    Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
    Type: Application
    Filed: March 26, 2002
    Publication date: July 25, 2002
    Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
  • Publication number: 20020085418
    Abstract: The present invention provides a nonvolatile memory system whose storage capacity can be easily changed. The nonvolatile memory system comprises plural memory modules, a controller for controlling the operation of the plural memory modules according to access requests from the outside, and a module selecting decoder for selectively enabling the memory modules by decoding a selection signal outputted from the controller, wherein the memory modules are freely mounted or dismounted. With this arrangement, the storage capacity can be changed by increasing or decreasing the memory modules.
    Type: Application
    Filed: December 21, 2001
    Publication date: July 4, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Hiroyuki Goto, Shigemasa Shiota, Takayuki Tamura, Hirofumi Shibuya, Yasuhiro Nakamura
  • Publication number: 20020080650
    Abstract: In the conventional nonvolatile memory, it is not possible to determine the cause of the error is accidental or due to the degradation when the error is detect at the time of data read. Therefore, unnecessary substitute processing is performed, resulting in the exhaustion of the substitute area to shorten the life of the storage device.
    Type: Application
    Filed: December 18, 2001
    Publication date: June 27, 2002
    Inventors: Kunihiro Katayama, Takayuki Tamura, Yusuke Jono, Motoki Kanamori, Atsushi Shikata
  • Publication number: 20020059191
    Abstract: A database operation processor according to this invention includes a self-join detector for detecting if a self-join operation is included in a query statement for a table in a database and generating a self-join operation expression, a join key classifier for classifying a join key included in a join condition in the operation expression into an equi-join key or a non equi-join key based on the generated self-join operation expression, and a self-join operation executor for sorting records stored in the table by the equi-join key, inputting in the sorted table, executing the generated self-join operation expression, and producing a result for the query statement.
    Type: Application
    Filed: July 5, 2001
    Publication date: May 16, 2002
    Inventor: Takayuki Tamura
  • Patent number: 6388920
    Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: May 14, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Kunihiro Katayama, Takayuki Tamura, Satoshi Watatani, Kiyoshi Inoue, Shigemasa Shiota, Masashi Naito
  • Publication number: 20020034306
    Abstract: A storage medium and an information processing system utilizing that storage medium capable of outputting information stored on the storage medium in a format unusable by other information devices or storage mediums. A storage medium and an information processing system utilizing that storage medium further capable of transferring information stored on the storage medium rather than copying the information so that the uniqueness of the information is assured. A storage medium comprised of a storage device for storing information, information required for encryption and encrypted information, and an I/F device for inputting and outputting information, information required for coding and store encrypted information in a storage device or from an external apparatus other than the storage device, and an encoding device for coding of information and decoding of encoded information.
    Type: Application
    Filed: September 4, 2001
    Publication date: March 21, 2002
    Inventors: Toru Owada, Jun Kitahara, Takeshi Asahi, Takayuki Tamura, Nagamasa Mizushima, Ikuya Kawaski, Takashi Totsuka