Abstract: An information processing apparatus is provided which is capable of carrying out the higher memory access. The information processing apparatus includes a memory unit of a synchronous DRAM device which serves to output data synchronously with the supplied clock signal, and a control unit for controlling the access to the memory unit in accordance with an instruction issued from a CPU. The clock signal which is to be supplied to the memory unit is outputted from the control unit. The clock signal which has been outputted from the control unit is supplied to the memory unit and also is pulled back to the control unit. The control unit fetches therein the data, which has been outputted from the storage unit, at the timing which is determined on the basis of the pulled back clock signal. As a result, the control unit reduces the difference between a delay of the data which is outputted from the control unit and a delay of the clock signal which is used to determine the timing at which the data is fetched therein.

Abstract: An information processing apparatus having a work suspend/resume function which allows operator to use a main memory shared by different processings even when work suspension information is saved therein. A system for allowing a same operational environment as that set up in one information processing apparatus to be easily implemented in another information processing apparatus. A main memory used by a CPU for execution of processings has a function for storing information concerning the state of the information processing apparatus prevailing at a time point when execution of a given processing is suspended by a CPU for allowing the suspended processing to be performed in continuation later on. When the suspension state information has already been stored in the main memory by a former user, the suspension state information is transferred to a removable nonvolatile storage device so that the CPU can perform other processing than the suspended one by using the main memory.

Abstract: High speed memory access and transparent error detection and correction using a single error correcting means are obtained. A host computer writes (2N-1)th (odd-numbered) sector data in one of the first memory and second memory (e.g., constituted by one or more memories) and 2N-th (even-numbered) sector data in the other of the first and second memory. Accordingly, (2N-1)th sector data can be read out from one of the first memory and second memory to the host computer, and at the same time (i.e., simultaneously), 2N-th sector data (i.e., next sector data to be read by the host computer) can be read out from the other of the first memory and second memory and error detection and correction can be performed in the error correcting means. Also, during a next cycle, the 2N-th (even-numbered) sector data read out from one of the first memory and second memory can be outputted to the host computer, and at the same time (i.e.

Abstract: An on-vehicle receiving system for optimizing the receiving performance of a radio receiver and a remote controlled receiver, whereby a remote-controlled receiver and a radio receiver share an on-vehicle antenna. A key detector for detecting whether an ignition key is fitted into a key cylinder of the vehicle is employed and a selector switch for connecting the on-vehicle antenna selectively to the remote-controlled receiver or the radio receiver are incorporated. When the key detector detects that the ignition key is fitted into the key cylinder, the selector switch selects the radio receiver. When it is detected that the ignition key is not fitted into the key cylinder, the remote-controlled receiver is selected. In one embodiment, a remote-controlled receiver and a radio receiver share not only an on-vehicle antenna but also part of receiving equipment. The remote-controlled receiver and radio receiver can also share the frequency and modulation form employed.