Patents by Inventor Takayuki Tsutsui

Takayuki Tsutsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11227862
    Abstract: An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit is formed including a plurality of protection diodes that are formed on the substrate and that are connected in series with each other, the protection circuit being connected to an output terminal of the amplifier circuit. A pad conductive layer is formed that at least partially includes a pad for connecting to a circuit outside the substrate. An insulating protective film covers the pad conductive layer. The insulating protective film includes an opening that exposes a partial area of a surface of the pad conductive layer, and that covers another area. A first bump is formed on the pad conductive layer on a bottom surface of the opening, and a second bump at least partially overlaps the protection circuit in plan view and is connected to a ground (GND) potential connected to the amplifier circuit.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: January 18, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenji Sasaki, Takayuki Tsutsui, Isao Obu, Yasuhisa Yamamoto
  • Patent number: 11196394
    Abstract: A power amplifier module includes a first substrate and a second substrate, at least part of the second substrate being disposed in a region overlapping the first substrate. The second substrate includes a first amplifier circuit and a second amplifier circuit. The first substrate includes a first transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; a second transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; and multiple first conductors disposed in a row between the first transformer and the second transformer, each of the multiple first conductors extending from the wiring layer on a first main surface to the wiring layer on a second main surface of the substrate.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: December 7, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shigeki Koya, Yasunari Umemoto, Yuichi Saito, Isao Obu, Takayuki Tsutsui
  • Patent number: 11164963
    Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: November 2, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Shigeki Koya, Masao Kondo, Takayuki Tsutsui
  • Publication number: 20210320194
    Abstract: A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer.
    Type: Application
    Filed: June 22, 2021
    Publication date: October 14, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Isao OBU, Yasunari UMEMOTO, Takayuki TSUTSUI, Satoshi TANAKA
  • Publication number: 20210305951
    Abstract: A power amplifier circuit includes a first amplifier that amplifies a first RF signal and outputs a second RF signal, a second amplifier that amplifies the second RF signal and outputs a third RF signal, a bias circuit that supplies a bias current or voltage to the first or second amplifier, and a bias adjustment circuit that adjusts the bias current or voltage on the basis of the first RF signal, the second RF signal, or the third RF signal. The bias adjustment circuit includes a first diode having an anode to which a control signal indicating a signal based on the first, second, or third RF signal is inputted, and a cathode connected to a ground. The bias circuit includes a bias transistor that outputs the bias current or voltage on the basis of a voltage at the anode of the first diode.
    Type: Application
    Filed: March 29, 2021
    Publication date: September 30, 2021
    Inventors: Takayuki TSUTSUI, Satoshi TANAKA
  • Publication number: 20210242843
    Abstract: A power amplifier circuit includes a first transistor that amplifies a first signal and outputs a second signal; a second transistor that amplifies the second signal and outputs a third signal; a bias circuit that supplies a bias current to a base of the second transistor; and a bias adjustment circuit that adjusts the bias current by subjecting the first signal to detection. The bias adjustment circuit controls the bias current such that a first current extracted from the bias circuit depends on a magnitude of the first signal.
    Type: Application
    Filed: April 23, 2021
    Publication date: August 5, 2021
    Inventors: Takayuki TSUTSUI, Masao KONDO, Satoshi TANAKA
  • Publication number: 20210235392
    Abstract: A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.
    Type: Application
    Filed: April 13, 2021
    Publication date: July 29, 2021
    Inventors: Satoshi TANAKA, Kiichiro TAKENAKA, Takayuki TSUTSUI, Taizo YAMAWAKI, Shun IMAI
  • Patent number: 11075289
    Abstract: A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: July 27, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Takayuki Tsutsui, Satoshi Tanaka
  • Publication number: 20210194444
    Abstract: A semiconductor chip includes a plurality of transistor rows. Corresponding to the plurality of transistor rows, a first bump connected to a collector of the transistor is arranged, and a second bump connected to an emitter is arranged. The transistor rows are arranged along sides of a convex polygon. A first land and a second land provided in a circuit board are connected to the first bump and the second bump, respectively. A first impedance conversion circuit connects the first land and the signal output terminal. A plurality of transistors in the transistor row are grouped into a plurality of groups, and the first impedance conversion circuit includes a reactance element arranged for each of the groups.
    Type: Application
    Filed: December 16, 2020
    Publication date: June 24, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Masao KONDO, Kiichiro TAKENAKA, Satoshi TANAKA, Takayuki TSUTSUI
  • Publication number: 20210183854
    Abstract: A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.
    Type: Application
    Filed: March 1, 2021
    Publication date: June 17, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Isao OBU, Shigeki KOYA, Yasunari UMEMOTO, Takayuki TSUTSUI
  • Patent number: 11018639
    Abstract: A power amplifier circuit includes a first transistor that amplifies a first signal and outputs a second signal; a second transistor that amplifies the second signal and outputs a third signal; a bias circuit that supplies a bias current to a base of the second transistor; and a bias adjustment circuit that adjusts the bias current to be supplied by the bias circuit by subjecting the first signal to detection. The bias adjustment circuit controls the bias current to be supplied to the base of the second transistor by drawing, from the bias circuit, a current of a magnitude corresponding to a magnitude of the first signal. The current increases as the magnitude of the first signal increases.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: May 25, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takayuki Tsutsui, Masao Kondo, Satoshi Tanaka
  • Patent number: 11006371
    Abstract: A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: May 11, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Kiichiro Takenaka, Takayuki Tsutsui, Taizo Yamawaki, Shun Imai
  • Publication number: 20210135657
    Abstract: An active balun circuit includes first and second transistors having emitters electrically coupled to each other and configured to output differential signals and a circuit element coupled between the connection point of the emitter of the first transistor and the emitter of the second transistor and a reference potential. The impedance of the circuit element at a particular frequency of the input signal appears significantly larger than impedances at other frequencies. An input signal from an input terminal is inputted to the base of the first transistor. The reference potential is applied to the base of the second transistor. A supply voltage is applied to the collector of the first transistor and the collector of the second transistor. A signal from the collector of the first transistor and a signal from the collector of the second transistor are outputted as the differential signals.
    Type: Application
    Filed: November 5, 2020
    Publication date: May 6, 2021
    Inventors: Takayuki TSUTSUI, Satoshi TANAKA, Kiichiro TAKENAKA, Masatoshi HASE
  • Publication number: 20210134788
    Abstract: A semiconductor device includes a plurality of unit transistors that are arranged on a surface of a substrate in a first direction. Input capacitive elements are arranged so as to correspond to the unit transistors. An emitter common wiring line is connected to emitter layers of the unit transistors. A via-hole extending from the emitter common wiring line to a back surface of the substrate is disposed at a position overlapping the emitter common wiring line. A collector common wiring line is connected to collector layers of the unit transistors. The input capacitive elements, the emitter common wiring line, the unit transistors, and the collector common wiring line are arranged in this order in a second direction. Base wiring lines that connect the input capacitive elements to base layers of the corresponding unit transistors intersect the emitter common wiring line without physical contact.
    Type: Application
    Filed: January 15, 2021
    Publication date: May 6, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Shigeki KOYA, Takayuki TSUTSUI, Kazuhito NAKAI, Yusuke TANAKA
  • Patent number: 10985123
    Abstract: A first wiring is disposed above operating regions of plural unit transistors formed on a substrate. A second wiring is disposed above the substrate. An insulating film is disposed on the first and second wirings. First and second cavities are formed in the insulating film. As viewed from above, the first and second cavities entirely overlap with the first and second wirings, respectively. A first bump is disposed on the insulating film and is electrically connected to the first wiring via the first cavity. A second bump is disposed on the insulating film and is electrically connected to the second wiring via the second cavity. As viewed from above, at least one of the plural operating regions is disposed within the first bump and is at least partially disposed outside the first cavity. The planar configuration of the first cavity and that of the second cavity are substantially identical.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: April 20, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi Kurokawa, Masayuki Aoike, Takayuki Tsutsui
  • Patent number: 10972060
    Abstract: In a radio frequency power amplifier, a semiconductor chip includes at least one first transistor amplifying a radio frequency signal, a first external-connection conductive member connected to the first transistor, a bias circuit including a second transistor that applies a bias voltage to the first transistor, and a second external-connection conductive member connected to the second transistor. The second external-connection conductive member at least partially overlaps with the second transistor when viewed in plan.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: April 6, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenji Sasaki, Isao Obu, Takayuki Tsutsui
  • Patent number: 10964693
    Abstract: A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: March 30, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Shigeki Koya, Yasunari Umemoto, Takayuki Tsutsui
  • Patent number: 10957617
    Abstract: A semiconductor chip includes an active element on a first surface of a substrate. A heat-conductive film having a higher thermal conductivity than the substrate is disposed at a position different from a position of the active element. An insulating film covering the active element and heat-conductive film is disposed on the first surface. A bump electrically connected to the heat-conductive film is disposed on the insulating film. A via-hole extends from a second surface opposite to the first surface to the heat-conductive film. A heat-conductive member having a higher thermal conductivity than the substrate is continuously disposed from a region of the second surface overlapping the active element in plan view to an inner surface of the via-hole. The bump is connected to a land of a printed circuit board facing the first surface. The semiconductor chip is sealed with a resin.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: March 23, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masao Kondo, Isao Obu, Yasunari Umemoto, Yasuhisa Yamamoto, Masahiro Shibata, Takayuki Tsutsui
  • Patent number: 10923470
    Abstract: A semiconductor device includes a plurality of unit transistors that are arranged on a surface of a substrate in a first direction. Input capacitive elements are arranged so as to correspond to the unit transistors. An emitter common wiring line is connected to emitter layers of the unit transistors. A via-hole extending from the emitter common wiring line to a back surface of the substrate is disposed at a position overlapping the emitter common wiring line. A collector common wiring line is connected to collector layers of the unit transistors. The input capacitive elements, the emitter common wiring line, the unit transistors, and the collector common wiring line are arranged in this order in a second direction. Base wiring lines that connect the input capacitive elements to base layers of the corresponding unit transistors intersect the emitter common wiring line without physical contact.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: February 16, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shigeki Koya, Takayuki Tsutsui, Kazuhito Nakai, Yusuke Tanaka
  • Publication number: 20210044256
    Abstract: A power amplifier module includes a first amplifier circuit that amplifies a radio frequency signal with a first gain corresponding to a first control signal to generate a first amplified signal; a second amplifier circuit that amplifies the first amplified signal with a second gain corresponding to a second control signal to generate a second amplified signal; and a control unit that generates the first control signal and the second control signal. The second control signal is a control signal for increasing a power-supply voltage for the second amplifier circuit as a peak-to-average power ratio of the radio frequency signal increases. The first control signal is a control signal for controlling the first gain of the first amplifier circuit so that a variation in the second gain involved in a variation in the power-supply voltage for the second amplifier circuit is compensated for.
    Type: Application
    Filed: October 28, 2020
    Publication date: February 11, 2021
    Inventors: Shigeki KOYA, Takayuki TSUTSUI, Yasunari UMEMOTO, Isao OBU, Satoshi TANAKA