Patents by Inventor Takayuki Tsutsui

Takayuki Tsutsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220256477
    Abstract: A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.
    Type: Application
    Filed: February 23, 2022
    Publication date: August 11, 2022
    Inventors: Satoshi TANAKA, Kiichiro TAKENAKA, Takayuki TSUTSUI, Taizo YAMAWAKI, Shun IMAI
  • Publication number: 20220200542
    Abstract: A power amplifier comprising a first member and a second member including a compound semiconductor region joined to a first face of the first member including a semiconductor region. The second member includes an amplifier circuit including a compound semiconductor element, and multiple clamp diodes connected in multiple stages and between an output port of the amplifier circuit and ground. The first member includes a switch, connected between an extension point, which is a middle point of the multiple clamp diodes and the ground, a temperature sensor, and a switch control circuit which performs on-off control of the switch based on a result of measurement by the temperature sensor. The extension point is connected to the switch via a path including an inter-member connection wire on an interlayer insulating film from the first face of the first member to a surface of the second member.
    Type: Application
    Filed: December 14, 2021
    Publication date: June 23, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Takayuki TSUTSUI, Masao KONDO
  • Patent number: 11368131
    Abstract: A power amplifier circuit amplifies a radio-frequency signal in a transmit frequency band. The power amplifier circuit includes an amplifier, a bias circuit, and an impedance circuit. The amplifier amplifies power of a radio-frequency signal and outputs an amplified signal. The impedance circuit is connected between a signal input terminal of the amplifier and a bias-current output terminal of the bias circuit and has frequency characteristics in which attenuation is obtained in the transmit frequency band. The impedance circuit includes first and second impedance circuits. The first impedance circuit is connected to the signal input terminal. The second impedance circuit is connected between the first impedance circuit and the bias-current output terminal.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: June 21, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takayuki Tsutsui, Satoshi Tanaka, Yasuhisa Yamamoto
  • Publication number: 20220189936
    Abstract: A semiconductor device includes first member that includes a switch made of a semiconductor element made from an elemental semiconductor. The first member is joined to a second member including a radio-frequency circuit including a semiconductor element made from a compound semiconductor. The switch and the radio-frequency circuit are connected by a path. The path includes an inter-member connection wire made of a metal pattern arranged on an interlayer insulating film extending from a surface of the second member to a surface of the first member or a conductive member allowing a current to flow in a direction crossing an interface where the first member and the second member are joined.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 16, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Takayuki TSUTSUI, Yuichi SAITO
  • Publication number: 20220157808
    Abstract: A semiconductor having transistors arranged side by side in one direction over a surface of a substrate and are connected in parallel. At least one passive element is disposed on at least one of regions between two adjacent ones of the transistors. The transistors each include a collector layer over the substrate, a base layer on the collector layer, and an emitter layer on the base layer. Collector electrodes are arranged in such a manner that each of the collector electrodes is located between the substrate and the collector layer of the corresponding one of the transistors and is electrically connected to the collector layer.
    Type: Application
    Filed: October 18, 2021
    Publication date: May 19, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Shinnosuke TAKAHASHI, Masayuki AOIKE, Takayuki TSUTSUI, Shigeki KOYA
  • Patent number: 11322462
    Abstract: A plurality of unit transistors that are connected in parallel to each other are formed on a substrate. In addition, a ground bump is provided on the substrate. A plurality of first capacitors are each provided for a corresponding one of the plurality of unit transistors and each connect an output electrode of the corresponding one of the plurality of unit transistors and the ground bump to each other.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: May 3, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takayuki Tsutsui, Isao Obu
  • Patent number: 11309852
    Abstract: A power amplifier includes initial-stage and output-stage amplifier circuits, and initial-stage and output-stage bias circuits. The initial-stage amplifier circuit includes a first high electron mobility transistor having a source electrically connected to a reference potential, and a gate to which a radio-frequency input signal is inputted, and a first heterojunction bipolar transistor having an emitter electrically connected to a drain of the first high electron mobility transistor, a base electrically connected to the reference potential in an alternate-current fashion, and a collector to which direct-current power is supplied and from which a radio-frequency signal is outputted.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: April 19, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Isao Obu, Satoshi Tanaka, Takayuki Tsutsui, Yasunari Umemoto
  • Publication number: 20220103143
    Abstract: A power amplification circuit includes first wiring supplied with a first signal having a first frequency, second wiring supplied with a second signal having a second frequency that differs from the first frequency, a first amplification circuit that amplifies the first signal supplied through the first wiring and supplies a first amplified signal to the second wiring, and a second amplification circuit that amplifies the signal supplied through the second wiring and outputs a second amplified signal.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 31, 2022
    Inventors: Shigeki KOYA, Takayuki TSUTSUI
  • Patent number: 11290964
    Abstract: A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: March 29, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Satoshi Tanaka, Kiichiro Takenaka, Takayuki Tsutsui, Taizo Yamawaki, Shun Imai
  • Patent number: 11289434
    Abstract: A semiconductor element includes a semiconductor substrate, first and second amplifiers provided on the semiconductor substrate and adjacently provided in a first direction, a first reference potential bump provided on a main surface of the semiconductor substrate, and connecting the first amplifier and a reference potential, a second reference potential bump provided on the main surface, being adjacent to the first reference potential bump in the first direction, and connecting the second amplifier and a reference potential, and a rectangular bump provided on the main surface, provided between the first and second reference potential bumps in a plan view, and formed such that a second width in a second direction orthogonal to the first direction is larger than a first width in the first direction. The second width is larger than a width of at least one of the first and second reference potential bumps in the second direction.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: March 29, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shigeki Koya, Yasunari Umemoto, Isao Obu, Masao Kondo, Yuichi Saito, Takayuki Tsutsui
  • Patent number: 11276689
    Abstract: A semiconductor device includes two cell rows, each of which is formed of a plurality of transistor cells aligned in parallel to each other. Each of the plurality of transistor cells includes a collector region, a base region, and an emitter region that are disposed above a substrate. A plurality of collector extended wiring lines are each connected to the collector region of a corresponding one of the plurality of transistor cells and are extended in a direction intersecting an alignment direction of the plurality of transistor cells. A collector integrated wiring line connects the plurality of collector extended wiring lines to each other. A collector intermediate integrated wiring line that is disposed between the two cell rows in plan view connects the plurality of collector extended wring lines extended from the plurality of transistor cells that belong to one of the two cell rows to each other.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: March 15, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenji Sasaki, Masao Kondo, Shigeki Koya, Shinnosuke Takahashi, Yasunari Umemoto, Isao Obu, Takayuki Tsutsui
  • Publication number: 20220060157
    Abstract: A radio-frequency amplifier circuit includes a first amplifier transistor configured to amplify and output a radio-frequency signal supplied to a base of the first amplifier transistor, a first bias transistor that is connected to the first amplifier transistor to form a current mirror and configured to supply a bias to the base of the first amplifier transistor, a second bias transistor that is connected to the base of the first amplifier transistor to form an emitter follower and configured to supply a bias to the base of the first amplifier transistor, and a first capacitor having a first end connected to the base of the first amplifier transistor and a second end connected to an emitter of the second bias transistor.
    Type: Application
    Filed: July 13, 2021
    Publication date: February 24, 2022
    Inventors: Takayuki TSUTSUI, Satoshi TANAKA
  • Publication number: 20220060158
    Abstract: A power amplifier module includes a first substrate and a second substrate, at least part of the second substrate being disposed in a region overlapping the first substrate. The second substrate includes a first amplifier circuit and a second amplifier circuit. The first substrate includes a first transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; a second transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; and multiple first conductors disposed in a row between the first transformer and the second transformer, each of the multiple first conductors extending from the wiring layer on a first main surface to the wiring layer on a second main surface of the substrate.
    Type: Application
    Filed: November 8, 2021
    Publication date: February 24, 2022
    Inventors: Shigeki KOYA, Yasunari UMEMOTO, Yuichi SAITO, Isao OBU, Takayuki TSUTSUI
  • Publication number: 20220029004
    Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.
    Type: Application
    Filed: October 6, 2021
    Publication date: January 27, 2022
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Isao OBU, Yasunari UMEMOTO, Masahiro SHIBATA, Shigeki KOYA, Masao KONDO, Takayuki TSUTSUI
  • Patent number: 11227862
    Abstract: An amplifier circuit including a semiconductor element is formed on a substrate. A protection circuit is formed including a plurality of protection diodes that are formed on the substrate and that are connected in series with each other, the protection circuit being connected to an output terminal of the amplifier circuit. A pad conductive layer is formed that at least partially includes a pad for connecting to a circuit outside the substrate. An insulating protective film covers the pad conductive layer. The insulating protective film includes an opening that exposes a partial area of a surface of the pad conductive layer, and that covers another area. A first bump is formed on the pad conductive layer on a bottom surface of the opening, and a second bump at least partially overlaps the protection circuit in plan view and is connected to a ground (GND) potential connected to the amplifier circuit.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: January 18, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenji Sasaki, Takayuki Tsutsui, Isao Obu, Yasuhisa Yamamoto
  • Patent number: 11196394
    Abstract: A power amplifier module includes a first substrate and a second substrate, at least part of the second substrate being disposed in a region overlapping the first substrate. The second substrate includes a first amplifier circuit and a second amplifier circuit. The first substrate includes a first transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; a second transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; and multiple first conductors disposed in a row between the first transformer and the second transformer, each of the multiple first conductors extending from the wiring layer on a first main surface to the wiring layer on a second main surface of the substrate.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: December 7, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Shigeki Koya, Yasunari Umemoto, Yuichi Saito, Isao Obu, Takayuki Tsutsui
  • Patent number: 11164963
    Abstract: A bipolar transistor includes a collector layer, a base layer, and an emitter layer that are formed in this order on a compound semiconductor substrate. The emitter layer is disposed inside an edge of the base layer in plan view. A base electrode is disposed on partial regions of the emitter layer and the base layer so as to extend from an inside of the emitter layer to an outside of the base layer in plan view. An insulating film is disposed between the base electrode and a portion of the base layer, with the portion not overlapping the emitter layer. An alloy layer extends from the base electrode through the emitter layer in a thickness direction and reaches the base layer. The alloy layer contains at least one element constituting the base electrode and elements constituting the emitter layer and the base layer.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: November 2, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Isao Obu, Yasunari Umemoto, Masahiro Shibata, Shigeki Koya, Masao Kondo, Takayuki Tsutsui
  • Publication number: 20210320194
    Abstract: A first sub-collector layer functions as an inflow path of a collector current that flows in a collector layer of a heterojunction bipolar transistor. A collector ballast resistor layer having a lower doping concentration than the first sub-collector layer is disposed between the collector layer and the first sub-collector layer.
    Type: Application
    Filed: June 22, 2021
    Publication date: October 14, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Isao OBU, Yasunari UMEMOTO, Takayuki TSUTSUI, Satoshi TANAKA
  • Publication number: 20210305951
    Abstract: A power amplifier circuit includes a first amplifier that amplifies a first RF signal and outputs a second RF signal, a second amplifier that amplifies the second RF signal and outputs a third RF signal, a bias circuit that supplies a bias current or voltage to the first or second amplifier, and a bias adjustment circuit that adjusts the bias current or voltage on the basis of the first RF signal, the second RF signal, or the third RF signal. The bias adjustment circuit includes a first diode having an anode to which a control signal indicating a signal based on the first, second, or third RF signal is inputted, and a cathode connected to a ground. The bias circuit includes a bias transistor that outputs the bias current or voltage on the basis of a voltage at the anode of the first diode.
    Type: Application
    Filed: March 29, 2021
    Publication date: September 30, 2021
    Inventors: Takayuki TSUTSUI, Satoshi TANAKA
  • Publication number: 20210242843
    Abstract: A power amplifier circuit includes a first transistor that amplifies a first signal and outputs a second signal; a second transistor that amplifies the second signal and outputs a third signal; a bias circuit that supplies a bias current to a base of the second transistor; and a bias adjustment circuit that adjusts the bias current by subjecting the first signal to detection. The bias adjustment circuit controls the bias current such that a first current extracted from the bias circuit depends on a magnitude of the first signal.
    Type: Application
    Filed: April 23, 2021
    Publication date: August 5, 2021
    Inventors: Takayuki TSUTSUI, Masao KONDO, Satoshi TANAKA