Abstract: The invention proposes a system that interrupts a processing associated with an ADC having low priority when an ADC processing cannot catch up with ADR by an ADC alone that is not under execution but uses an ADC for an ADR having high priority. To preferentially execute ADR/ADC having high priority, the invention employs an algorithm for serially selecting ADR/ADC in the order of higher processing capacity (in the order of greater numerical values in the expression by a DPH unit) from among ADR/ADCs that have the lowest priority, no matter whether the ADR/DC is now under execution or not.

Abstract: The present invention relates to a method of detecting cancer by use of an oncogene, a method of screening for an active compound useful to treat and/or prevent cancer, and a pharmaceutical composition for treatment and/or prevention of cancer. More specifically, the present invention provides a method of detecting cancer based on the expression of the human oculospanin gene as a marker and a pharmaceutical composition containing an antibody capable of specifically recognizing human oculospanin and having cytotoxic activity against cancer cells.

Abstract: The present invention relates to an inspection device and inspection method of a specimen, particularly to the inspection device and inspection method of defects of semiconductor wafers, and the object is to cope with the increase of inspection images and provide an inspection device and inspection method which is capable of classification by sub class, meeting the user needs, in addition to the automatic classification by an inspection device.

Abstract: An NMIS gate implantation layer is generated by a method in which mask data of a P-type well implantation layer are added to mask data obtained by subtracting mask data of an NMIS-SD implantation layer and PMIS-SD implantation layer from mask data of an N-type well implantation layer. In a CMOS device fabricating process, ions are implanted into a polysilicon film by using the NMIS gate implantation layer, resulting in reduction in the total numbers of PN junctions and non-doped regions in a gate polysilicon film.

Abstract: A classification model optimum for realization of a defect classification request by a user is not known by the user. Then, the user sets a classification model which is not necessarily suitable and makes classification, resulting in degradation in classification performance. Therefore, the present invention automatically generates plural potential classification models and combines class likelihoods calculated from the plural classification models to classify. To combine, an index about the adequacy of each model, in other words, an index indicating a reliable level of likelihood calculated from the each potential classification model, is also calculated. Considering the calculated result, the class likelihoods calculated from the plural classification models are combined to execute classification.

Abstract: In a silicon layer formed on an insulator layer, a lattice defect region is formed to be adjacent to a channel region and source/drain regions, and the lower part of the channel region functions as a high-concentration channel region. The holes of hole-electron pairs generated in the channel region are eliminated by recombination in the lattice defect region, thereby suppressing the bipolar operation resulting from the accumulation of holes and increasing the source/drain breakdown voltage. The threshold value of a parasitic transistor is increased by the high-concentration channel region so as to reduce the leakage current in the OFF state. Alternatively, the holes may be moved to the source region to disappear therein by providing, instead of the lattice defect region, a high-concentration diffusion layer constituting and operating as a pn diode between the channel and source regions.

Abstract: A semiconductor device according to the present invention includes: a semiconductor substrate including an active region and an isolation region; an MIS transistor formed in the active region; a trench isolation structure formed in the isolation region; an insulating film covering both the MIS transistor and the trench isolation structure; and an interlevel dielectric film formed on the insulating film. An opening, which reaches part of source/drain doped regions of the MIS transistor and part of the trench isolation structure, is formed in the interlevel dielectric film. An electrode is formed to be in contact with the source/drain doped regions through the opening. The insulating film is made of a material making the insulating film function as etch stop layer for the interlevel dielectric film. A stepped portion is formed between the respective upper surfaces of the active region and the trench isolation structure. At least one of the source/drain doped regions reaches a side of the stepped portion.

Abstract: In a silicon layer formed on an insulator layer, a lattice defect region is formed to be adjacent to a channel region and source/drain regions, and the lower part of the channel region functions as a high-concentration channel region. The holes of hole-electron pairs generated in the channel region are eliminated by recombination in the lattice defect region, thereby suppressing the bipolar operation resulting from the accumulation of holes and increasing the source/drain breakdown voltage. The threshold value of a parasitic transistor is increased by the high-concentration channel region so as to reduce the leakage current in the OFF state. Alternatively, the holes may be moved to the source region to disappear therein by providing, instead of the lattice defect region, a high-concentration diffusion layer constituting and operating as a pn diode between the channel and source regions.

Abstract: In a silicon layer formed on an insulator layer, a lattice defect region is formed to be adjacent to a channel region and source/drain regions, and the lower part of the channel region functions as a high-concentration channel region. The holes of hole-electron pairs generated in the channel region are eliminated by recombination in the lattice defect region, thereby suppressing the bipolar operation resulting from the accumulation of holes and increasing the source/drain breakdown voltage. The threshold value of a parasitic transistor is increased by the high-concentration channel region so as to reduce the leakage current in the OFF state. Alternatively, the holes may be moved to the source region to disappear therein by providing, instead of the lattice defect region, a high-concentration diffusion layer constituting and operating as a pn diode between the channel and source regions.

Abstract: The present invention relates to an inspection device and inspection method of a specimen, particularly to the inspection device and inspection method of defects of semiconductor wafers, and the object is to cope with the increase of inspection images and provide an inspection device and inspection method which is capable of classification by sub class, meeting the user needs, in addition to the automatic classification by an inspection device.

Abstract: A method for classifying defects includes imaging an inspected object. An image of a defect candidate is extracted from an image obtained by said imaging step. Said extracted defect candidate image is classified into a first category. Said extracted defect candidate image is classified into a second category. Said extracted defect candidate image and information relating to said classification into said first category and information relating to said classification into said second category are displayed on a screen.

Abstract: A semiconductor fabrication control monitor includes a first conducting film having a first area, a second area, a third area and a fourth area mutually connected, a first electrode, a second electrode, a third electrode and a fourth electrode all formed on a semiconductor substrate. The first electrode is formed from a second conducting film formed above the first area with an insulating film sandwiched therebetween. The second electrode is formed from the second conducting film formed above the second area with the insulating film sandwiched therebetween. The third electrode is formed from the second conducting film formed above and in direct contact with the third area. The fourth electrode is formed from the second conducting film formed above and in direct contact with the fourth area. The first electrode and the second electrode are mutually connected through a connecting part of the second conducting film, and are electrically connected to the first conducting film.

Abstract: In an active area surrounded with an isolation formed on a silicon substrate, a large number of unit cells are disposed in a matrix, and the unit cell together form one MOSFET. Each of the unit includes a ring gate electrode in the shape of a regular octagon, a drain region and a source region formed at the inside and outside of the gate electrode, respectively, two gate withdrawn wires extending from the gate electrode to area above the isolation, a substrate contact portion in which the surface of the substrate is exposed, and contacts for electrically connecting these elements with wires. These elements such as the ring gate electrode and the gate withdrawn wires are formed so as to attain a high frequency characteristic as good as possible. Thus a MOSFET for use in a high frequency signal device, the high frequency characteristic such as the minimum noise figure and the maximum oscillation frequency in particular can be totally improved.

Abstract: In forming a P.sup.- body diffused layer in a portion on the source side of an N.sup.- drain diffused layer of a DMOSFET, P-type impurity ions are implanted at a large tilt angle to reach a part of a region underlying an N.sup.+ gate electrode by using, as a mask, a resist film having an opening corresponding to a region in which the body diffused layer of the DMOSFET is to be formed and the N.sup.+ gate electrode so as to be activated. Thereafter, an N.sup.+ source diffused layer and an N.sup.+ drain diffused layer are formed in the P.sup.- body diffused layer and in the N.sup.- drain diffused layer, respectively. Since a high-temperature drive-in process need not be performed to introduce the P-type impurity ions into the region underlying the N.sup.+ gate electrode, a reduction or variations in threshold voltage and the degradation of a gate oxide film each caused by the impurity diffused from the N.sup.+ gate electrode can be prevented.

Abstract: In a semiconductor apparatus having a PNP bipolar transistor and high voltage resistance, there is formed an oxide insulating layer in the surface region of a P-type semiconductor substrate. In the above semiconductor substrate is formed a P-type collector layer so that at least a part of the P-type collector layer is in contact with said oxide insulating layer. In the surface region of said P-type collector layer is formed a P-type collector contact layer. An N-type base layer is formed in that region on the surface side of said P-type collector layer in which said P-type collector contact layer does not exist. A P-type emitter layer is formed on the surface side of said N-type base layer.

Abstract: An n-type buried layer and an n-type epitaxial layer that becomes a collector layer of a pnp transistor are formed on a semiconductor substrate. A well and the collector layer are formed. Ions of an n-type impurity are implanted through a photoresist mask, to form an intrinsic base layer of the pnp transistor and a PT-VT diffusion layer with punchthrough stopper and threshold control functions of a pMOSFET. Ions of a p-type impurity are implanted through a photoresist mask at a shallow implantation depth than the previous step, to form an intrinsic base layer of an npn transistor and a channel dope layer of the pMOSFET. A buried channel is formed under the gate of the pMOSFET. Therefore pMOSFETs with good characteristics can be obtained. In this way, the present invention achieves bipolar transistors and MOSFETs with good characteristics, without having to increase the number of fabrication steps and the number of photoresist masks.

Abstract: A silicon oxide film and a polysilicon film are formed on a silicon substrate and are selectively etched to form a contact hole in a region where an emitter is to be formed. A polysilicon film is laid on the substrate and two polysilicon films are patterned to form an emitter electrode and a gate electrode made of the two polysilicon films which are doped with arsenic. The arsenic is diffused from the polysilicon films of the emitter electrode into the silicon substrate to form an N.sup.+ emitter layer which has a high concentration and is shallow. Consequently, the contamination of a gate insulator film can be prevented from occurring and a bipolar transistor having high performance, for example, a high current amplification factor or the like can be formed.

Abstract: In forming a P.sup.- body diffused layer in a portion on the source side of an N.sup.- drain diffused layer of a DMOSFET, P-type impurity ions are implanted at a large tilt angle to reach a part of a region underlying an N.sup.+ gate electrode by using, as a mask, a resist film having an opening corresponding to a region in which the body diffused layer of the DMOSFET is to be formed and the N.sup.+ gate electrode so as to be activated. Thereafter, an N.sup.+ source diffused layer and an N.sup.+ drain diffused layer are formed in the P.sup.- body diffused layer and in the N.sup.- drain diffused layer, respectively. Since a high-temperature drive-in process need not be performed to introduce the P-type impurity ions into the region underlying the N.sup.+ gate electrode, a reduction or variations in threshold voltage and the degradation of a gate oxide film each caused by the impurity diffused from the N.sup.+ gate electrode can be prevented.

Abstract: Mounted on a single semiconductor substrate are a DRAM, MOS transistor, resistor, and capacitor. The gate electrode of the DRAM and the gate electrode of the MOS transistor are formed by a common layer (i.e., a first-level poly-Si layer). The storage electrode of the DRAM. the resistor, and the lower electrode of the capacitor are formed by a common layer (i.e., a third-level poly-Si layer). The plate electrode of the DRAM and the upper electrode of the capacitor are formed by a common layer (i.e., a fourth-level poly-Si layer).

Abstract: In a semiconductor apparatus having a PNP bipolar transistor and high voltage resistance, there is formed an oxide insulating layer in the surface region of a P-type semiconductor substrate. In the above semiconductor substrate is formed a P-type collector layer so that at least a part of the P-type collector layer is in contact with said oxide insulating layer. In the surface region of said P-type collector layer is formed a P-type collector contact layer. An N-type base layer is formed in that region on the surface side of said P-type collector layer in which said P-type collector contact layer does not exist. A P-type emitter layer is formed on the surface side of said N-type base layer.