Patents by Inventor Takehiro Hirai

Takehiro Hirai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5696006
    Abstract: A silicon oxide film and a polysilicon film are formed on a silicon substrate and are selectively etched to form a contact hole in a region where an emitter is to be formed. A polysilicon film is laid on the substrate and two polysilicon films are patterned to form an emitter electrode and a gate electrode made of the two polysilicon films which are doped with arsenic. The arsenic is diffused from the polysilicon films of the emitter electrode into the silicon substrate to form an N.sup.+ emitter layer which has a high concentration and is shallow. Consequently, the contamination of a gate insulator film can be prevented from occurring and a bipolar transistor having high performance, for example, a high current amplification factor or the like can be formed.
    Type: Grant
    Filed: August 2, 1996
    Date of Patent: December 9, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takehiro Hirai, Masahiro Nakatani, Mitsuo Tanaka, Akihiro Kanda
  • Patent number: 5406106
    Abstract: A silicon oxide film as a dielectric film and a silicon nitride film or a polysilicon film as a protection film for the silicon oxide film are formed on a silicon substrate. After the two films are selectively etched to form contact holes of a bipolar transistor, a polysilicon film as a conductive film is laid on the entire substrate and selectively etched to form electrodes. In a MIS transistor, the protection film of the silicon nitride film serves as a gate insulator film and the protection film of the polysilicon film serves as a gate electrode. Accordingly, contamination to the gate insulator film at formation of contact holes of the bipolar transistor is prevented, and an excellent semiconductor with Bi-MOS structure is manufactured with low cost.
    Type: Grant
    Filed: June 15, 1993
    Date of Patent: April 11, 1995
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takehiro Hirai, Masahiro Nakatani, Mitsuo Tanaka, Akihiro Kanda
  • Patent number: 5331198
    Abstract: The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1) . The IIL comprises an emitter, a base and a collector which are respectively comprised of a high-density n.sup.+ -type first buried layer (5), a p.sup.+ -type second buried layer (8) having a lower impurity density than the n.sup.+ -type first buried layer (5), and at least one of n.sup.+ -type diffused layer (31). The semiconductor device thus constituted makes it possible to increase the emitter injection efficiency while the base impurity density is kept high, and also to decrease the base width, so that the collector-emitter breakdown voltage and current gain of the IIL can be more improved and also the operation speed of the IIL can be made higher.
    Type: Grant
    Filed: August 5, 1992
    Date of Patent: July 19, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiro Kanda, Mitsuo Tanaka, Takehiro Hirai, Masahiro Nakatani
  • Patent number: 5323054
    Abstract: In a a semiconductor device having a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same substrate, grooves that reach an n.sup.+ -type buried layer 5 serving as an emitter of the IIL and an n.sup.+ -type buried layer 4 serving as a collector of the vertical npn transistor are formed at the same time, and an oxide film 101 is formed only on the sidewall of each groove; in the grooves, n.sup.+ -type polycrystalline silicon films 103 and 102 are formed, which are made to serve as an emitter lead-out portion of the IIL and a collector wall of the vertical npn transistor, respectively; a p-type diffused layer 17 serving as an injector of the IIL and a p-type diffused layer 18 and p.sup.
    Type: Grant
    Filed: July 1, 1992
    Date of Patent: June 21, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiro Kanda, Mitsuo Tanaka, Takehiro Hirai, Masahiro Nakatani
  • Patent number: 5318917
    Abstract: A method of fabricating a semiconductor device includes the steps of forming a base diffusion layer in a predetermined region in a semiconductor substrate of a first conduction type, the base diffusion layer being of a second conduction type; forming first insulating films and simultaneously forming an emitter lead-out electrode and a collector lead-out electrode in regions above an emitter-contact-forming region and a collector-contact-forming region, the first insulating films extending on the emitter and collector lead-out electrodes, the emitter and collector lead-out electrodes including impurity corresponding to the first conduction type; forming second insulating films at sides of the emitter and collector lead-out electrodes; forming a base contact; forming a base lead-out electrode including impurity corresponding to the second conduction type; diffusing the impurity from the emitter lead-out electrode, the collector lead-out electrode, and the base lead-out electrode to form an emitter diffusion lay
    Type: Grant
    Filed: February 10, 1993
    Date of Patent: June 7, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiro Kanda, Yoshiro Fujita, Takehiro Hirai, Mitsuo Tanaka, Hideya Esaki
  • Patent number: 5204274
    Abstract: A method of fabricating a semiconductor device includes the steps of forming a base diffusion layer in a predetermined region in a semiconductor substrate of a first conduction type, the base diffusion layer being of a second conduction type; forming first insulating films and simultaneously forming an emitter lead-out electrode and a collector lead-out electrode in regions above an emitter-contact-forming region and a collector-contact-forming region, the first insulating extending films on the emitter and collector lead-out electrodes, the emitter and collector lead-out electrodes including impurity corresponding to the first conduction type; forming second insulating films at sides of the emitter and collector lead-out electrodes; forming a base contact; forming a base lead-out electrode including impurity corresponding to the second conduction type; diffusing the impurity from the emitter lead-out electrode, the collector lead-out electrode, and the base lead-out electrode to form an emitter diffusion lay
    Type: Grant
    Filed: August 29, 1991
    Date of Patent: April 20, 1993
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiro Kanda, Yoshiro Fujita, Takehiro Hirai, Mitsuo Tanaka, Hideya Esaki
  • Patent number: 5162252
    Abstract: The present invention provides a semiconductor device, in particular, a semiconductor device comprising a vertical npn transistor, a vertical pnp transistor and an IIL which are integrated on the same one-conductivity type semiconductor substrate (1). The IIL comprises an emitter, a base and a collector which are respectively comprised of a high-density n.sup.+ -type first buried layer (5), a p.sup.+ -type second buried layer (8) having a lower impurity density than the n.sup.+ -type first buried layer (5), and at least one of n.sup.+ -type diffused layer (31).The semiconductor device thus constituted makes it possible to increase the emitter injection efficiency while the base impurity density is kept high, and also to decrease the base width, so that the collector-emitter breakdown voltage and current gain of the IIL can be more improved and also the operation speed of the IIL can be made higher.
    Type: Grant
    Filed: December 17, 1991
    Date of Patent: November 10, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akihiro Kanda, Mitsuo Tanaka, Takehiro Hirai, Masahiro Nakatani