Patents by Inventor Takehisa Sasabayashi

Takehisa Sasabayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210074482
    Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and layered internal electrodes, first and second main surfaces, first and second side surfaces, first and second end surfaces, and an external electrode connected to the internal electrodes and provided on each of the first and second end surfaces. A region where the internal electrodes are superimposed is defined as an effective region, regions respectively located on sides of the first and second end surfaces relative to the effective region are defined as first and second regions, and a bent portion where the dielectric layers and the internal electrodes are bent is located in the first region. In the bent portion, all vertices in the stacking direction are located within a range that extends by about 25 ?m to about 35 ?m in a length direction from the effective region of the multilayer body.
    Type: Application
    Filed: August 24, 2020
    Publication date: March 11, 2021
    Inventors: Shinichi KOKAWA, Yasuyuki SHIMADA, Naoto MURANISHI, Takehisa SASABAYASHI
  • Publication number: 20210020380
    Abstract: A multilayer electronic component includes a multilayer body including dielectric layers and inner electrode layers. Each of the dielectric layers includes first crystal grains defining and functioning as plate-shaped objects that have an average thickness of less than or equal to about 300 nm and an average aspect ratio of more than or equal to about 5, each of the inner electrode layers includes second crystal grains defining and functioning as plate-shaped objects that have an average thickness of less than or equal to about 150 nm and an average aspect ratio of more than or equal to about 5, where an aspect ratio is represented by a ratio of a major axis of each plate-shaped object to a thickness of the plate-shaped object with the major axis of the plate-shaped object being orthogonal or substantially orthogonal to a thickness direction of the plate-shaped object.
    Type: Application
    Filed: July 16, 2020
    Publication date: January 21, 2021
    Inventors: Takehisa SASABAYASHI, Kiyoshiro ISHIBE, Kenji UENO, Ai FUKUMORI, Akihiro TSURU, Daisuke HAMADA
  • Publication number: 20210020376
    Abstract: A multilayer electronic component having a plurality of laminated dielectric layers and inner electrode layers. The dielectric layers have a plurality of crystal grains including first regions where Re is dissolved in a solid state; and second regions where Re is not dissolved in the solid state. A median size of the crystal grains to an average thickness of the dielectric layers is 0.5?t?0.7. A ratio of a sum of cross sectional areas of the first regions to those of the plurality of crystal grains is 0.7?s?0.9. When a total amount of Ti, Zr, and Hf is 100 molar parts in the dielectric layers, a sum of the Zr and the Hf is 0?a?1.0; an amount b of Si is 0.1?b?1.0; an amount c of Re is 0.5?c?10.0; and a ratio m of a total of Ba and Re to a total of Ti, Zr, and Hf is 0.990?m?1.050.
    Type: Application
    Filed: June 30, 2020
    Publication date: January 21, 2021
    Inventors: Takehisa Sasabayashi, Kenjiro Gomi, Kenji Kimura, Wataru Oshima
  • Publication number: 20200273623
    Abstract: A multilayer ceramic capacitor includes a ceramic body including a stack of dielectric layers and internal electrodes, and an external electrode electrically connected to each of the internal electrodes and provided at each of both end surfaces of the ceramic body. The external electrode includes a metal layer and a plating layer on the metal layer. In a cross section of the metal layer that is obtained by cutting the external electrode along a plane parallel to a side surface at a central position in a width direction, the metal layer includes a dielectric material at an area ratio of about 20% or more, and includes cavities at an area ratio of about 5% or more and about 20% or less, the cavities having an average diameter of about 0.5 ?m or more and about 1.5 ?m or less, and having a maximum diameter of about 5.0 ?m or less.
    Type: Application
    Filed: February 12, 2020
    Publication date: August 27, 2020
    Inventors: Takehisa SASABAYASHI, Akitaka DOI, Kotaro SHIMIZU, Yoko OKABE
  • Publication number: 20200105468
    Abstract: An electronic component includes a laminate including internal electrodes alternately laminated in a lamination direction with dielectric layers interposed therebetween. The laminate includes main surfaces opposite to each other in the lamination direction, side surfaces opposite to each other in a width direction, and end surfaces opposite to each other in a length direction, and external electrodes provided on surfaces of the laminate and electrically connected to the internal electrodes. Each of the dielectric layers includes Ti and Mg. When a cross section including the length direction and the width direction of the laminate is viewed from the lamination direction, side margin portions in which the internal electrodes do not exist each include a dielectric including Ti and Mg with a molar ratio in each of the side margin portions smaller than a molar ratio of Mg to Ti included in each of the dielectric layers.
    Type: Application
    Filed: September 11, 2019
    Publication date: April 2, 2020
    Inventors: Hideyuki HASHIMOTO, Daiki FUKUNAGA, Takayuki YAO, Takehisa SASABAYASHI
  • Patent number: 10535468
    Abstract: A method for manufacturing a multilayer ceramic capacitor includes preparing a green multilayer body including a stack of dielectric sheets printed with inner electrodes, coating the green multilayer body with a conductive paste that is connected to the inner electrodes, and firing the conductive paste and the green multilayer body at the same time, wherein a rate of temperature increase from about 800° C. to about 1,100° C. during the firing is about 15° C. per minute or more.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: January 14, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takehisa Sasabayashi, Yasuhiro Nishisaka, Satoshi Matsuno, Yoko Okabe
  • Patent number: 10014110
    Abstract: A multilayer ceramic capacitor includes an external electrode that is unlikely to be peeled. First and second external electrodes each include base layers provided over a ceramic body and including a metal and glass, and Cu plated layers provided over the base layers. The multilayer ceramic capacitor includes a reactive layer. The reactive layer contains about 5 atomic % to about 15 atomic % of Ti, about 5 atomic % to about 15 atomic % of Si, and about 2 atomic % to about 10 atomic % of V.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: July 3, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasuhiro Nishisaka, Takehisa Sasabayashi, Satoshi Muramatsu
  • Publication number: 20180108483
    Abstract: A method for manufacturing a multilayer ceramic capacitor includes preparing a green multilayer body including a stack of dielectric sheets printed with inner electrodes, coating the green multilayer body with a conductive paste that is connected to the inner electrodes, and firing the conductive paste and the green multilayer body at the same time, wherein a rate of temperature increase from about 800° C. to about 1,100° C. during the firing is about 15° C. per minute or more.
    Type: Application
    Filed: October 16, 2017
    Publication date: April 19, 2018
    Inventors: Takehisa SASABAYASHI, Yasuhiro NISHISAKA, Satoshi MATSUNO, Yoko OKABE
  • Patent number: 9881739
    Abstract: A multilayer ceramic capacitor provided in a multilayer printed wiring board includes a ceramic body with a plurality of ceramic layers and internal electrodes stacked, and an external electrode including a base layer that includes a sintered metal containing a metal and glass and a plated layer provided on the surface of the base layer, which is provided on an end surface of the ceramic body to be connected to the internal electrodes. The external electrode includes a principal surface portion disposed on a principal surface of the ceramic body. The outermost layer of the plated layer includes a Cu plated layer. The ratio of arithmetic mean roughness (Ra) at the surface of the ceramic body/arithmetic mean roughness (Ra) at the surface of the external electrode satisfies a condition: about 0.06?the arithmetic mean roughness (Ra) at the surface of the ceramic body/the arithmetic mean roughness (Ra) at the surface of the external electrode?about 0.97.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: January 30, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takehisa Sasabayashi
  • Publication number: 20170330690
    Abstract: A conductive paste that includes conductive particles and a solvent. The solvent has a Hansen solubility parameter with an SP value of 24 to 39, a hydrogen bond term ?h of 15 or more, and a polarity term ?p of 7 or more. The conductive paste is applied to an unfired laminated body having laminated ceramic green sheets and internal electrode layers.
    Type: Application
    Filed: May 3, 2017
    Publication date: November 16, 2017
    Inventors: Akitaka Doi, Takehisa Sasabayashi, Naoaki Ogata
  • Publication number: 20170178809
    Abstract: A multilayer ceramic capacitor includes an external electrode that is unlikely to be peeled. First and second external electrodes each include base layers provided over a ceramic body and including a metal and glass, and Cu plated layers provided over the base layers. The multilayer ceramic capacitor includes a reactive layer. The reactive layer contains about 5 atomic % to about 15 atomic % of Ti, about 5 atomic % to about 15 atomic % of Si, and about 2 atomic % to about 10 atomic % of V.
    Type: Application
    Filed: March 2, 2017
    Publication date: June 22, 2017
    Inventors: Yasuhiro NISHISAKA, Takehisa SASABAYASHI, Satoshi MURAMATSU
  • Patent number: 9627136
    Abstract: A multilayer ceramic capacitor includes an external electrode that is unlikely to be peeled. First and second external electrodes each include base layers provided over a ceramic body and including a metal and glass, and Cu plated layers provided over the base layers. The multilayer ceramic capacitor includes a reactive layer. The reactive layer contains about 5 atomic % to about 15 atomic % of Ti, about 5 atomic % to about 15 atomic % of Si, and about 2 atomic % to about 10 atomic % of V.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: April 18, 2017
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasuhiro Nishisaka, Takehisa Sasabayashi, Satoshi Muramatsu
  • Patent number: 9607763
    Abstract: A monolithic ceramic electronic component includes a component body and outer electrodes. The component body includes a plurality of stacked ceramic layers and a plurality of inner electrodes which extend between the ceramic layers, which contain Ni, and which include exposed ends exposed on predetermined surfaces of the component body. The outer electrodes are electrically connected to the exposed ends of the inner electrodes and are formed on the predetermined surfaces of the component body by plating. The inner electrodes include Mg—Ni coexistence regions where Mg and Ni coexist.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: March 28, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takehisa Sasabayashi, Akihiro Motoki, Makoto Ogawa
  • Patent number: 9343234
    Abstract: A monolithic ceramic electronic component includes an outer electrode including a first plating layer formed directly on a component body by electroless plating so as to cover an exposed portion distribution region including exposed portions of a plurality of inner electrodes and a second plating layer formed by electrolytic plating so as to cover the first plating layer. An amount of extension of the first plating E1 and an amount of extension of the second plating E2 satisfy the relationship E1/(E1+E2)?20%, where E1 represents a distance from an edge of the exposed portion distribution region to an edge of the first plating layer, and E2 represents a distance from the edge of the first plating layer to an edge of the second plating layer.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: May 17, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Takehisa Sasabayashi, Akihiro Motoki, Makoto Ogawa
  • Publication number: 20160093438
    Abstract: A multilayer ceramic capacitor provided in a multilayer printed wiring board includes a ceramic body with a plurality of ceramic layers and internal electrodes stacked, and an external electrode including a base layer that includes a sintered metal containing a metal and glass and a plated layer provided on the surface of the base layer, which is provided on an end surface of the ceramic body to be connected to the internal electrodes. The external electrode includes a principal surface portion disposed on a principal surface of the ceramic body. The outermost layer of the plated layer includes a Cu plated layer. The ratio of arithmetic mean roughness (Ra) at the surface of the ceramic body/arithmetic mean roughness (Ra) at the surface of the external electrode satisfies a condition: about 0.06 the arithmetic mean roughness (Ra) at the surface of the ceramic body/the arithmetic mean roughness (Ra) at the surface of the external electrode about 0.97.
    Type: Application
    Filed: September 28, 2015
    Publication date: March 31, 2016
    Inventor: Takehisa SASABAYASHI
  • Publication number: 20160093440
    Abstract: A multilayer ceramic capacitor includes an external electrode that is unlikely to be peeled. First and second external electrodes each include base layers provided over a ceramic body and including a metal and glass, and Cu plated layers provided over the base layers. The multilayer ceramic capacitor includes a reactive layer. The reactive layer contains about 5 atomic % to about 15 atomic % of Ti, about 5 atomic % to about 15 atomic % of Si, and about 2 atomic % to about 10 atomic % of V.
    Type: Application
    Filed: September 28, 2015
    Publication date: March 31, 2016
    Inventors: Yasuhiro NISHISAKA, Takehisa SASABAYASHI, Satoshi MURAMATSU
  • Publication number: 20140293503
    Abstract: A monolithic ceramic electronic component includes an outer electrode including a first plating layer formed directly on a component body by electroless plating so as to cover an exposed portion distribution region including exposed portions of a plurality of inner electrodes and a second plating layer formed by electrolytic plating so as to cover the first plating layer. An amount of extension of the first plating E1 and an amount of extension of the second plating E2 satisfy the relationship E1/(E1+E2)?20%, where E1 represents a distance from an edge of the exposed portion distribution region to an edge of the first plating layer, and E2 represents a distance from the edge of the first plating layer to an edge of the second plating layer.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 2, 2014
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Takehisa SASABAYASHI, Akihiro MOTOKI, Makoto OGAWA
  • Publication number: 20140211369
    Abstract: A monolithic ceramic electronic component includes a component body and outer electrodes. The component body includes a plurality of stacked ceramic layers and a plurality of inner electrodes which extend between the ceramic layers, which contain Ni, and which include exposed ends exposed on predetermined surfaces of the component body. The outer electrodes are electrically connected to the exposed ends of the inner electrodes and are formed on the predetermined surfaces of the component body by plating. The inner electrodes include Mg—Ni coexistence regions where Mg and Ni coexist.
    Type: Application
    Filed: January 22, 2014
    Publication date: July 31, 2014
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Takehisa SASABAYASHI, Akihiro MOTOKI, Makoto OGAWA
  • Patent number: 8593785
    Abstract: A laminate includes insulating layers laminated to each other. Capacitor conductors are embedded in the laminate and have exposed portions exposed between the insulating layers at respective surfaces of the laminate. The capacitor conductors define a capacitor. External electrodes are provided by plating on the respective surfaces of the laminate so as to directly cover the respective exposed portions. When the laminate is viewed in plan in a y axis direction, the length of each of the exposed portions is approximately 35% to approximately 45% of the length of an outer periphery of the insulating layer.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: November 26, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Takehisa Sasabayashi, Takumi Taniguchi
  • Patent number: 8587919
    Abstract: In a laminate type ceramic electronic component, when an external electrode for a laminated ceramic capacitor is formed directly by plating onto a surface of a component main body, the film that is directly plated may have a low fixing strength with respect to the component main body. As the external electrode, a first plating layer composed of a Ni—P plating film with a P content rate of about 9 weight % or more is first formed such that a plating deposition deposited with the exposed ends of respective internal electrodes as starting points is grown on at least an end surface of a component main body. Then, a second plating layer composed of a Ni plating film containing substantially no P is formed on the first plating layer. Preferably, the first plating layer is formed by electroless plating, whereas the second plating layer is formed by electrolytic plating.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: November 19, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Makoto Ogawa, Akihiro Motoki, Takehisa Sasabayashi, Takayuki Kayatani