Abstract: A boron diffusion region is formed at a surface of a silicon substrate. A pair of n-type source/drain regions are formed at a surface of boron diffusion region. A gate electrode is formed at a region located between paired source/drain regions with a gate insulating film therebetween. A nitrogen implanted region is formed at the surface of silicon substrate located between paired n-type source/drain regions. Nitrogen implanted region has a peak nitrogen concentration at a position of a depth not exceeding 500 Å from the surface of silicon substrate. Thereby, a transistor structure which can be easily miniaturized can be obtained.

Abstract: A TFT of the present invention includes an insulating substrate, a first conductive film layer which is to be a gate electrode provided on the insulating substrate, a first insulating film layer which is to be a gate insulating film layer provided on the first conductive film layer, a non-doped semiconductor layer formed on the first insulating film layer, and a second conductive film layer which is to be a source electrode formed on a source region of the semiconductor layer and a drain electrode formed on a drain region of the semiconductor, wherein a junction is formed by implanting an n-type impurity in the source region of the semiconductor layer and the drain region of the semiconductor.

Abstract: An object of the present invention is to easily search for shops having delivery areas including user terminals. When two users access a shop search site of a server by use of user terminals (step S1), the same contents are displayed on both of the user terminals in the following processing: One of the users is set as the merchandise purchaser (step S2), the position information of the other user, the merchandise receiver, is transmitted to the server (step S3), and the desired shop kind is set by one of the users (step S4). Then, shops of the shop kind the delivery areas of which include the receiver are retrieved and displayed.

Abstract: Broadcasting waves transmitted from a broadcasting device include operation control information for operating peripheral devices on a receiver side in accordance with the contents of a broadcast program in addition to broadcast data about said broadcast program. The receiver outputs the broadcast data to a display device, and transmits an operation command signal dependent on the operation control information to the peripheral devices to operate the peripheral devices in accordance with the contents of the broadcast program. As a result, an air conditioner raises or lowers room temperature and an illumination device blinks according to the progress of the program.

Abstract: The liquid crystal display of the present invention comprising: a gate electrode line formed on an insulating substrate; a source electrode line including a source electrode intersected with said gate electrode line via an insulating film, a thin film transistor located in a vicinity of a portion in which said gate electrode line is intersected with said source electrode line; two drain electrode lines, each including two drain electrodes in said thin film transistor, said drain electrode line being connected with a pixel electrode; wherein said thin film transistor includes said two drain electrode lines located on both sides of said source electrode; said two drain electrodes being formed at a place where each end portion of said two drain electrode lines opposed to said source electrode is superposed with said gate electrode line.

Abstract: A TFT of the present invention includes an insulating substrate, a first conductive film layer which is to be a gate electrode provided on the insulating substrate, a first insulating film layer which is to be a gate insulating film layer provided on the first conductive film layer, a non-doped semiconductor layer formed on the first insulating film layer, and a second conductive film layer which is to be a source electrode formed on a source region of the semiconductor layer and a drain electrode formed on a drain region of the semiconductor, wherein a junction is formed by implanting an n-type impurity in the source region of the semiconductor layer and the drain region of the semiconductor.

Abstract: A boron diffusion region is formed at a surface of a silicon substrate. A pair of n-type source/drain regions are formed at a surface of boron diffusion region. A gate electrode is formed at a region located between paired source/drain regions with a gate insulating film therebetween. A nitrogen implanted region is formed at the surface of silicon substrate located between paired n-type source/drain regions. Nitrogen implanted region has a peak nitrogen concentration at a position of a depth not exceeding 500 .ANG. from the surface of silicon substrate. Thereby, a transistor structure which can be easily miniaturized can be obtained.

Abstract: An electronic flash is provided with a detector for detecting a voltage of a power source when a charging of a capacitor is started, a timer for measuring an elapsed time from the start of the charging, a memory for storing a relationship between control times and voltages of the power source, and a controller for setting a control time based on a detected voltage and the stored relationship, and controlling stop of the charging in accordance with the set control time and measurement of the timer. This can prevent excessive charging without unnecessarily making the capacitor larger.

Abstract: In order to obtain a semiconductor device having an internal wire of low resistance, a conductive layer whose surface is silicified is provided in a surface of a semiconductor substrate. A conductor whose surface is silicified is provided on the semiconductor substrate in proximity to the conductive layer. This semiconductor device is provided with an internal wiring layer, which is formed by a titanium film and a titanium silicide layer for electrically connecting the surface of the conductive layer and a surface of an end of the conductor with each other, to cover a side wall surface and a bottom surface of a contact hole.

Abstract: A semiconductor memory device and a manufacturing method of the same can effectively prevent deterioration of endurance characteristic which may occur in a data erasing operation, and a drain disturb phenomenon which may occur in a data writing operation. In the semiconductor memory device, an N-type impurity layer 3 is formed on a main surface of a P-type silicon substrate 1 located in a channel region. Thereby, a high electric field is not applied to a boundary region between the N-type impurity layer 3 and an N-type source diffusion region 10 during erasing of data, so that generation of interband tunneling in this region is effectively prevented. Also in this semiconductor memory device, the drain diffusion region 9 has an offset structure in which no portion thereof overlaps the floating gate electrode 5.

Abstract: A trench for element isolation is formed on the main surface of a semiconductor substrate. A conductive layer is formed in the trench, electrically connected to the semiconductor substrate. Oxide films and a dielectric film is formed between the conductive layer and the sidewall of the trench. A field oxide film is formed on the conductive layer. The dielectric film extends from the sidewall of the field oxide film to a region between the sidewall of the trench and the conductive layer. Consequently, a semiconductor device having an element isolation structure of superior isolation capability and high reliability can be obtained.

Abstract: A boron diffusion region is formed at a surface of a silicon substrate. A pair of n-type source/drain regions are formed at a surface of boron diffusion region. A gate electrode is formed at a region located between paired source/drain regions with a gate insulating film therebetween. A nitrogen implanted region is formed at the surface of silicon substrate located between paired n-type source/drain regions. Nitrogen implanted region has a peak nitrogen concentration at a position of a depth not exceeding 500 .ANG. from the surface of silicon substrate. Thereby, a transistor structure which can be easily miniaturized can be obtained.

Abstract: In order to obtain a semiconductor device having an internal wire of low resistance, a conductive layer whose surface is silicified is provided in a surface of a semiconductor substrate. A conductor whose surface is silicified is provided on the semiconductor substrate in proximity to the conductive layer. This semiconductor device is provided with an internal wiring layer, which is formed by a titanium film and a titanium silicide layer for electrically connecting the surface of the conductive layer and a surface of an end of the conductor with each other, to cover a side wall surface and a bottom surface of a contact hole.

Abstract: A semiconductor memory device and a manufacturing method of the same can effectively prevent deterioration of endurance characteristic which may occur in a data erasing operation, and a drain disturb phenomenon which may occur in a data writing operation. In the semiconductor memory device, an N-type impurity layer 3 is formed on a main surface of a P-type silicon substrate 1 located in a channel region. Thereby, a high electric field is not applied to a boundary region between the N-type impurity layer 3 and an N-type source diffusion region 10 during erasing of data, so that generation of interband tunneling in this region is effectively prevented. Also in this semiconductor memory device, the drain diffusion region 9 has an offset structure in which no portion thereof overlaps the floating gate electrode 5.

Abstract: A memory cell of a DRAM comprises one MOS transistor and one capacitor. The MOS transistor includes a pair of source/drain regions and a gate electrode formed on the channel region. A bit line is formed so as to be connected to the source/drain region. A conductive layer is formed so as to be connected to the source/drain region. The gate electrode includes a first part formed on the channel region with an oxide film interposedand second and third parts extending from the first part, respectively, and formed on the bit line and the conductive layer with an interlayer oxide film interposed. The capacitor includes a lower electrode formed so as to be connected to the conductive layer and an upper electrode formed so as to be opposed to the surface of the lower electrode with a dielectric film interposed. The upper electrode is placed above the bit line. A word line is placed above the upper electrode and connected to the gate electrode.

Abstract: Access transistors of memory cells in a DRAM are formed in a solid phrase epitaxial single crystalline layer on the surface of a silicon substrate. A bit line extending over the surface of an element isolation and insulation film is formed by patterning a polycrystalline silicon layer extending to the single crystalline silicon layer as a layer. A stacked capacitor is connected to one source/drain of the access transistor through a conductive layer extending to the single crystalline silicon layer and over a field oxide film. Part of the stacked capacitor extends over the bit line. The connection region of the bit line, the capacitor and the source/drain is formed above the element isolation and insulation film, so that the source/drain region of the access transistor can be reduced.

Abstract: An MIS transistor includes insulating layers formed by the CVD method as gate insulating layers. The gate insulating layers by the CVD method are formed having a uniform film thickness on the channel region surface roughed by etching treatment or the like. The dielectric breakdown strength of the gate insulating layer is thus assured.

Abstract: A semiconductor device manufacturing apparatus has a first space and a second space in a process chamber in which a semiconductor wafer is accommodated, the first and second spaces being separated by the semiconductor wafer. A process gas port opens into the first space adjacent to the obverse surface of the semiconductor wafer, and an infrared light transmission window is formed in a wall of the chamber at the second space facing the reverse surface of the semiconductor wafer. No layers are deposited on the reverse surface of the semiconductor wafer and the infrared light transmission window so that the emissivity at the reverse surface of the semiconductor wafer is not changed during layer deposition. The temperature during processing can therefore be monitored accurately with a pyrometer, and a reduction in the transmissivity of the window is prevented.

Abstract: Each memory cell of a dynamic random access memory comprises a semiconductor layer of a first conductivity type, one and the other impurity regions of a second conductivity type, a gate electrode, a capacitor impurity region of the first conductivity type, and a capacitor electrode. The semiconductor layer of the first conductivity type comprises a first surface and a second surface located opposite to the first surface. One and the other impurity regions are formed spaced apart from each other in the semiconductor layer so as to define a channel region with a channel surface being a part of the first surface of the semiconductor layer. The gate electrode is formed on the channel surface through a gate insulating film. The capacitor impurity region is formed opposing to the channel region, near the second surface of the semiconductor layer and having a concentration higher than that of the semiconductor layer. The capacitor electrode is formed on the capacitor impurity region through a dielectric film.

Abstract: A field effect transistor including a gate electrode, a source electrode and a drain electrode which are formed on a major surface of a silicon substrate. An impurity contained in the source electrode and the drain electrode is diffused into the silicon substrate by heat treatment of thereby form source and drain areas of the transistor. The source electrode and the drain electrode are electrically insulated from the gate electrode by a side-wall insulating film. The side-wall insulating film and the gate insulating film are formed by separate steps, so can each be formed in optimum thickness.