Patents by Inventor Takehisa Yamaguchi

Takehisa Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5218217
    Abstract: Each memory cell of a dynamic random access memory comprises a semiconductor layer of a first conductivity type, one and the other impurity regions of a second conductivity type, a gate electrode, a capacitor impurity region of the first conductivity type, and a capacitor electrode. The semiconductor layer of the first conductivity type comprises a first surface and a second surface located opposite to the first surface. One and the other impurity regions are formed spaced apart from each other in the semiconductor layer so as to define a channel region with a channel surface being a part of the first surface of the semiconductor layer. The gate electrode is formed on the channel surface through a gate insulating film. The capacitor impurity region is formed opposing to the channel region, near the second surface of the semiconductor layer and having a concentration higher than that of the semiconductor layer. The capacitor electrode is formed on the capacitor impurity region through a dielectric film.
    Type: Grant
    Filed: August 16, 1990
    Date of Patent: June 8, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hidekazu Oda, Kiyoteru Kobayashi, Takehisa Yamaguchi
  • Patent number: 5144393
    Abstract: A field effect transistor including a gate electrode, a source electrode and a drain electrode which are formed on a major surface of a silicon substrate. An impurity contained in the source electrode and the drain electrode is diffused into the silicon substrate by heat treatment of thereby form source and drain areas of the transistor. The source electrode and the drain electrode are electrically insulated from the gate electrode by a side-wall insulating film. The side-wall insulating film and the gate insulating film are formed by separate steps, so can each be formed in optimum thickness.
    Type: Grant
    Filed: May 22, 1991
    Date of Patent: September 1, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takehisa Yamaguchi, Masahiro Shimizu
  • Patent number: 5134452
    Abstract: The MIS transistor according to the present invention includes insulating layers formed by the CVD method as gate insulating layers. The gate insulating layers formed by the CVD method have a uniform film thickness on the channel region surface roughened by etching treatment or the like. Thus, dielectric breakdown strength of the gate insulating layer is assured.
    Type: Grant
    Filed: March 29, 1991
    Date of Patent: July 28, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takehisa Yamaguchi, Masahiro Shimizu
  • Patent number: 4050120
    Abstract: A fastener is made of a flexible material for use, for example, in a vehicle to hold a leg member on a plate inserted in an opening in a panel. The fastener comprises a tubular base, a tubular inner portion formed within the base, and a connecting portion connecting the base and the inner portion. The connecting portion has an opening at its center to receive the leg member, there being an obliqued opening at the opposite end to furnish a water-proof connection.
    Type: Grant
    Filed: April 5, 1976
    Date of Patent: September 27, 1977
    Assignee: Kato Hatsujyo Co., Ltd.
    Inventor: Takehisa Yamaguchi