Patents by Inventor Takehito KOSHIZAWA
Takehito KOSHIZAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220013359Abstract: In an embodiment, a method for forming features for semiconductor processing. A first mandrel and a second mandrel are formed on a substrate. A first spacer is formed along a first sidewall of the first mandrel, and a second spacer is formed along a second sidewall of the second mandrel. A gap is defined between the first spacer and the second spacer. The gap is filled by a gap-filling material. In some examples, the gap-filling material includes a doped silicon material. In some examples, the first spacer and the second spacer each include a doped silicon material.Type: ApplicationFiled: August 27, 2021Publication date: January 13, 2022Inventors: Takehito KOSHIZAWA, Rui CHENG, Tejinder SINGH, Hidetaka OSHIO
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Publication number: 20210327891Abstract: Memory devices and methods of manufacturing memory devices are provided. A plasma enhanced chemical vapor deposition (PECVD) method to form a memory cell film stack having more than 50 layers as an alternative for 3D-NAND cells is described. The memory stack comprises alternating layers of a first material layer and a second material layer.Type: ApplicationFiled: April 6, 2021Publication date: October 21, 2021Applicant: Applied Materials, Inc.Inventors: Takehito Koshizawa, Bo Qi, Abhijit Basu Mallick, Huiyuan Wang, Susmit Singha Roy
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Patent number: 11145509Abstract: In an embodiment, a method for forming features for semiconductor processing. A first mandrel and a second mandrel are formed on a substrate. A first spacer is formed along a first sidewall of the first mandrel, and a second spacer is formed along a second sidewall of the second mandrel. A gap is defined between the first spacer and the second spacer. The gap is filled by a gap-filling material. In some examples, the gap-filling material includes a doped silicon material. In some examples, the first spacer and the second spacer each include a doped silicon material.Type: GrantFiled: April 20, 2020Date of Patent: October 12, 2021Assignee: Applied Materials, Inc.Inventors: Takehito Koshizawa, Rui Cheng, Tejinder Singh, Hidetaka Oshio
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Publication number: 20210257375Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming a plurality of nonvolatile memory cells, comprising forming, on a substrate, a stack of alternating layers of metal including a first layer of metal and a second layer of metal different from the first layer of metal; removing the first layer of metal to form spaces between the alternating layers of the second layer of metal; and one of depositing a first layer of material to partially fill the spaces to leave air gaps therein or depositing a second layer of material to fill the spaces.Type: ApplicationFiled: April 12, 2021Publication date: August 19, 2021Inventors: Takehito Koshizawa, Mukund Srinivasan, Tomohiko Kitajima, Chang Seok Kang, Sung-Kwan Kang, Gill Y. Lee, Susmit Singha Roy
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Publication number: 20210233918Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming a plurality of nonvolatile memory cells, comprising forming, on a substrate, a stack of alternating layers of metal including a first layer of metal and a second layer of metal different from the first layer of metal; removing the first layer of metal to form spaces between the alternating layers of the second layer of metal; and one of depositing a first layer of material to partially fill the spaces to leave air gaps therein or depositing a second layer of material to fill the spaces.Type: ApplicationFiled: April 12, 2021Publication date: July 29, 2021Inventors: Takehito Koshizawa, Mukund Srinivasan, Tomohiko Kitajima, Chang Seok Kang, Sung-Kwan Kang, Gill Y. Lee, Susmit Singha Roy
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Patent number: 11043372Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of high-density films for patterning applications. In one implementation, a method of processing a substrate is provided. The method includes flowing a hydrocarbon-containing gas mixture into a processing volume of a process chamber having a substrate positioned on an electrostatic chuck. The substrate is maintained at a pressure between about 0.5 mTorr and about 10 Torr. The method further includes generating a plasma at the substrate level by applying a first RF bias to the electrostatic chuck to deposit a diamond-like carbon film on the substrate. The diamond-like carbon film has a density greater than 1.8 g/cc and a stress less than ?500 MPa.Type: GrantFiled: May 15, 2018Date of Patent: June 22, 2021Assignee: Applied Materials, Inc.Inventors: Eswaranand Venkatasubramanian, Samuel E. Gottheim, Yang Yang, Pramit Manna, Kartik Ramaswamy, Takehito Koshizawa, Abhijit Basu Mallick, Srinivas Gandikota
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Publication number: 20210134807Abstract: Apparatuses and methods to provide a patterned substrate are described. A plurality of patterned and spaced first lines and carbon material lines and formed on the substrate surface by selectively depositing and etching films extending in a first direction and films extending in a second direction that crosses the first direction to pattern the underlying structures.Type: ApplicationFiled: January 12, 2021Publication date: May 6, 2021Applicant: Applied Materials, Inc.Inventors: Tejinder Singh, Takehito Koshizawa, Abhijit Basu Mallick, Pramit Manna, Nancy Fung, Eswaranand Venkatasubramanian, Ho-yung David Hwang, Samuel E. Gottheim
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Patent number: 10998329Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming a plurality of nonvolatile memory cells, comprising forming, on a substrate, a stack of alternating layers of metal including a first layer of metal and a second layer of metal different from the first layer of metal; removing the first layer of metal to form spaces between the alternating layers of the second layer of metal; and one of depositing a first layer of material to partially fill the spaces to leave air gaps therein or depositing a second layer of material to fill the spaces.Type: GrantFiled: July 22, 2019Date of Patent: May 4, 2021Assignee: APPLIED MATERIALS, INC.Inventors: Takehito Koshizawa, Mukund Srinivasan, Tomohiko Kitajima, Chang Seok Kang, Sung-Kwan Kang, Gill Y. Lee, Susmit Singha Roy
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Patent number: 10954129Abstract: A method of fabricating a semiconductor structure is described. The method comprises forming at least one mandrel on a substrate, the at least one mandrel comprising a diamond-like carbon and having a top and two opposing sidewalls, the diamond-like carbon comprising at least 40% sp3 hybridized carbon atoms. The mandrel may be used in Self-Aligned Multiple Patterning (SAMP) processes.Type: GrantFiled: June 7, 2018Date of Patent: March 23, 2021Assignee: Applied Materials, Inc.Inventors: Takehito Koshizawa, Eswaranand Venkatasubramanian, Pramit Manna, Chi Lu, Chi-I Lang, Nancy Fung, Abhijit Basu Mallick
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Publication number: 20210082936Abstract: Electronic devices and methods of forming the electronic devices are described. The electronic devices comprise a plurality of memory holes extending along a first direction through a plurality of alternating oxide and nitride layers. Each memory hole has a core oxide surrounded by a semiconductor material, the semiconductor material surrounded by a dielectric. The memory holes are staggered to provide a plurality of memory hole lines having spaced memory holes so that adjacent memory hole lines have the memory holes in a staggered configuration. A conductive material is on top of the stack of alternating oxide and nitride layers. A dielectric filled cut line extends through the conductive material in a direction across the plurality of memory hole lines. The dielectric filled cut line separates a first memory hole line from an adjacent second memory hole line without disabling the functionality of the memory holes.Type: ApplicationFiled: September 13, 2020Publication date: March 18, 2021Inventor: Takehito Koshizawa
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Publication number: 20210043449Abstract: Embodiments herein provide methods of depositing an amorphous carbon layer using a plasma enhanced chemical vapor deposition (PECVD) process and hard masks formed therefrom. In one embodiment, a method of processing a substrate includes positioning a substrate on a substrate support, the substrate support disposed in a processing volume of a processing chamber, flowing a processing gas comprising a hydrocarbon gas and a diluent gas into the processing volume, maintaining the processing volume at a processing pressure less than about 100 mTorr, igniting and maintaining a deposition plasma of the processing gas by applying a first power to one of one or more power electrodes of the processing chamber, maintaining the substrate support at a processing temperature less than about 350° C., exposing a surface of the substrate to the deposition plasma, and depositing an amorphous carbon layer on the surface of the substrate.Type: ApplicationFiled: April 8, 2019Publication date: February 11, 2021Inventors: Eswaranand VENKATASUBRAMANIAN, Yang YANG, Pramit MANNA, Kartik RAMASWAMY, Takehito KOSHIZAWA, Abhijit Basu MALLICK
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Publication number: 20210040618Abstract: Embodiments of the present disclosure relate to methods for depositing an amorphous carbon layer onto a substrate, including over previously formed layers on the substrate, using a plasma-enhanced chemical vapor deposition (PECVD) process, in particular, the methods described herein utilize a combination of RF AC power and pulsed DC power to create a plasma which deposits an amorphous carbon layer with power to create a plasma which deposits an amorphour carbon layer with a high ratio of sp3 (diamond-like) carbon to sp2 (graphite-like) carbon. The methods also provide for lower processing pressures, lower processing temperatures, and higher processing powers, each of which, alone or in combination, may further increase the relative fraction of sp3 carbon in the deposited amorphous carbon layer.Type: ApplicationFiled: October 16, 2018Publication date: February 11, 2021Inventors: Eswaranand VENKATASUBRAMANIAN, Yang YANG, Pramit MANNA, Kartik RAMASWAMY, Takehito KOSHIZAWA, Abhijit B. MALLICK
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Patent number: 10910381Abstract: Apparatuses and methods to provide a patterned substrate are described. A plurality of patterned and spaced first lines and carbon material lines and formed on the substrate surface by selectively depositing and etching films extending in a first direction and films extending in a second direction that crosses the first direction to pattern the underlying structures.Type: GrantFiled: July 31, 2019Date of Patent: February 2, 2021Assignee: Applied Materials, Inc.Inventors: Tejinder Singh, Takehito Koshizawa, Abhijit Basu Mallick, Pramit Manna, Nancy Fung, Eswaranand Venkatasubramanian, Ho-yung David Hwang, Samuel E. Gottheim
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Publication number: 20200373310Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming a plurality of nonvolatile memory cells, comprising forming, on a substrate, a stack of alternating layers of metal including a first layer of metal and a second layer of metal different from the first layer of metal; removing the first layer of metal to form spaces between the alternating layers of the second layer of metal; and one of depositing a first layer of material to partially fill the spaces to leave air gaps therein or depositing a second layer of material to fill the spaces.Type: ApplicationFiled: July 22, 2019Publication date: November 26, 2020Inventors: Takehito Koshizawa, Mukund Srinivasan, Tomohiko Kitajima, Chang Seok Kang, Sung-Kwan Kang, Gill Y. Lee, Susmit Singha Roy
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Publication number: 20200373159Abstract: In an embodiment, a method for forming features for semiconductor processing. A first mandrel and a second mandrel are formed on a substrate. A first spacer is formed along a first sidewall of the first mandrel, and a second spacer is formed along a second sidewall of the second mandrel. A gap is defined between the first spacer and the second spacer. The gap is filled by a gap-filling material. In some examples, the gap-filling material includes a doped silicon material. In some examples, the first spacer and the second spacer each include a doped silicon material.Type: ApplicationFiled: April 20, 2020Publication date: November 26, 2020Inventors: Takehito KOSHIZAWA, Rui CHENG, Tejinder SINGH, Hidetaka OSHIO
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Publication number: 20200043932Abstract: Apparatuses and methods to provide a patterned substrate are described. A plurality of patterned and spaced first lines and carbon material lines and formed on the substrate surface by selectively depositing and etching films extending in a first direction and films extending in a second direction that crosses the first direction to pattern the underlying structures.Type: ApplicationFiled: July 31, 2019Publication date: February 6, 2020Inventors: Tejinder Singh, Takehito Koshizawa, Abhijit Basu Mallick, Pramit Manna, Nancy Fung, Eswaranand Venkatasubramanian, Ho-yung David Hwang, Samuel E. Gottheim
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Patent number: 10403502Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of hardmask films on a substrate. In one implementation, a method of forming a hardmask layer on a substrate is provided. The method comprises forming a seed layer on a substrate by supplying a seed layer gas mixture in a processing chamber. The method further includes forming a transition layer comprising tungsten, boron and carbon on the seed layer by supplying a transition layer gas mixture in the processing chamber. The method further includes forming a bulk hardmask layer comprising tungsten, boron and carbon on the transition layer by supplying a main deposition gas mixture in the processing chamber.Type: GrantFiled: January 29, 2018Date of Patent: September 3, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Eswaranand Venkatasubramanian, Abhijit Basu Mallick, Susmit Singha Roy, Takehito Koshizawa
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Publication number: 20180358229Abstract: A method of fabricating a semiconductor structure is described. The method comprises forming at least one mandrel on a substrate, the at least one mandrel comprising a diamond-like carbon and having a top and two opposing sidewalls, the diamond-like carbon comprising at least 40% sp3 hybridized carbon atoms. The mandrel may be used in Self-Aligned Multiple Patterning (SAMP) processes.Type: ApplicationFiled: June 7, 2018Publication date: December 13, 2018Applicant: Applied Materials, Inc.Inventors: Takehito Koshizawa, Eswaranand Venkatasubramanian, Pramit Manna, Chi Lu, Chi-I Lang, Nancy Fung, Abhijit Basu Mallick
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Publication number: 20180218902Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits. More particularly, the implementations described herein provide techniques for deposition of hardmask films on a substrate. In one implementation, a method of forming a hardmask layer on a substrate is provided. The method comprises forming a seed layer on a substrate by supplying a seed layer gas mixture in a processing chamber. The method further includes forming a transition layer comprising tungsten, boron and carbon on the seed layer by supplying a transition layer gas mixture in the processing chamber. The method further includes forming a bulk hardmask layer comprising tungsten, boron and carbon on the transition layer by supplying a main deposition gas mixture in the processing chamber.Type: ApplicationFiled: January 29, 2018Publication date: August 2, 2018Inventors: Eswaranand VENKATASUBRAMANIAN, Abhijit Basu MALLICK, Susmit Singha ROY, Takehito KOSHIZAWA
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Patent number: 9508561Abstract: Embodiments of the present invention provide methods for forming an interconnection structure in semiconductor devices without breaking vacuum with minimum oxidation/atmosphere exposure. In one embodiment, a method for forming an interconnection structure for semiconductor devices includes supplying a barrier layer etching gas mixture into a first processing chamber having a substrate disposed therein to etch portions of a barrier layer exposed by a patterned metal layer until the underlying substrate is exposed, the first processing chamber disposed in a processing system, and forming a liner layer on the substrate covering the etched barrier layer in a second processing chamber disposed in the processing system.Type: GrantFiled: May 13, 2014Date of Patent: November 29, 2016Assignee: APPLIED MATERIALS, INC.Inventors: Mehul B. Naik, Srinivas D. Nemani, Takehito Koshizawa, He Ren