Abstract: Methods are described for forming “air gaps” between adjacent metal lines on patterned substrates. The common name “air gap” will be used interchangeably with the more technically accurate “gas pocket” and both reflect a variety of pressures and elemental ratios. The air gaps are produced within narrow gaps between copper lines while wide gaps retain dielectric material. Retention of the dielectric material within the wide gaps enables formation of a desirable planar top surface. Using a hardmask layer and a selective dry-etch process enables a wet processing step to be avoided right before the formation of the air gaps. The air gaps can have a dielectric constant approaching one, favorably reducing interconnect capacitance compared with typical low-k dielectric materials.

Abstract: Embodiments of the present invention provide methods for forming an interconnection structure in semiconductor devices without breaking vacuum with minimum oxidation/atmosphere exposure. In one embodiment, a method for forming an interconnection structure for semiconductor devices includes supplying a barrier layer etching gas mixture into a first processing chamber having a substrate disposed therein to etch portions of a barrier layer exposed by a patterned metal layer until the underlying substrate is exposed, the first processing chamber disposed in a processing system, and forming a liner layer on the substrate covering the etched barrier layer in a second processing chamber disposed in the processing system.

Abstract: Methods are described for forming “air gaps” between adjacent metal lines on patterned substrates. The common name “air gap” will be used interchangeably with the more technically accurate “gas pocket” and both reflect a variety of pressures and elemental ratios. The air gaps are produced within narrow gaps between copper lines while wide gaps retain dielectric material. Retention of the dielectric material within the wide gaps enables formation of a desirable planar top surface. Using a hardmask layer and a selective dry-etch process enables a wet processing step to be avoided right before the formation of the air gaps. The air gaps can have a dielectric constant approaching one, favorably reducing interconnect capacitance compared with typical low-k dielectric materials.

Abstract: Methods for etching a dielectric barrier layer disposed on the substrate using a low temperature etching process along with a subsequent interface protection layer deposition process are provided. In one embodiment, a method for etching a dielectric barrier layer disposed on a substrate includes transferring a substrate having a dielectric barrier layer disposed thereon into an etching processing chamber, performing a treatment process on the dielectric barrier layer, remotely generating a plasma in an etching gas mixture supplied into the etching processing chamber to etch the treated dielectric barrier layer disposed on the substrate, plasma annealing the dielectric barrier layer to remove the dielectric barrier layer from the substrate, and forming an interface protection layer after the dielectric barrier is removed from the substrate.

Abstract: In an apparatus and method for treating a wafer-shaped article, a rotary chuck is configured to hold a wafer-shaped article of a predetermined diameter such that a surface of the wafer-shaped article facing the rotary chuck is spaced from an opposing peripheral surface of the rotary chuck. The opposing peripheral surface comprises a first surface overlapping an outer peripheral edge of a wafer-shaped article when positioned on the spin chuck and a second surface positioned radially inwardly of the first surface and meeting the first surface at an interface that is radially inward of and substantially concentric with a wafer-shaped article when positioned on the rotary chuck. The second surface is substantially more hydrophobic than the first surface.