Patents by Inventor Takekazu Tanaka

Takekazu Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7224045
    Abstract: A leadless type semiconductor package includes a plate-like mount, and at least one semiconductor chip mounted on the plate-like mount such that a bottom surface of the semiconductor chip is secured to the plate-like mount, and the semiconductor chip has at least one electrode pad formed on a top surface thereof. The package further includes at least one flat electrode electrically connected to the electrode pad, and a molded resin enveloper for completely sealing and encapsulating the semiconductor chip. The molded resin enveloper further partially seals and encapsulates the flat electrode such that a part of the flat electrode is exposed as an outer electrode pad on a top surface of the molded resin enveloper.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: May 29, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Yukinori Tabira, Takekazu Tanaka
  • Publication number: 20070090499
    Abstract: In a semiconductor package including at least one plate-like mount, a semiconductor chip has at least one electrode formed on a top surface thereof, and is mounted on the plate-like mount such that a bottom surface of the semiconductor chip is in contact with the plate-like mount. The semiconductor package also includes at least one lead element having an outer portion arranged to be flush with the plate-like mount, and an inner portion deformed and shaped to overhang the semiconductor chip such that an inner end of the lead element is spaced apart from the top surface of the semiconductor chip. The semiconductor package further includes a bonding-wire element bonded at ends thereof to the electrode of the semiconductor chip and the inner end of the lead element, an enveloper sealing and encapsulating the plate-like mount, the semiconductor chip, the inner portion of the lead element, and the bonding-wire element.
    Type: Application
    Filed: October 4, 2006
    Publication date: April 26, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takekazu Tanaka
  • Patent number: 7189599
    Abstract: A lead frame of the present invention includes a pair of base portions having a substantially flat bottom each. An island portion and electrode portions are partly connected to the tops of the base portions. The lead frame needs a minimum of production cost and promotes dense mounting of semiconductor devices to a circuit board.
    Type: Grant
    Filed: September 9, 2004
    Date of Patent: March 13, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Takekazu Tanaka
  • Patent number: 7138673
    Abstract: In a semiconductor package including at least one plate-like mount, a semiconductor chip has at least one electrode formed on a top surface thereof, and is mounted on the plate-like mount such that a bottom surface of the semiconductor chip is in contact with the plate-like mount. The semiconductor package also includes at least one lead element having an outer portion arranged to be flush with the plate-like mount, and an inner portion deformed and shaped to overhang the semiconductor chip such that an inner end of the lead element is spaced apart from the top surface of the semiconductor chip. The semiconductor package further includes a bonding-wire element bonded at ends thereof to the electrode of the semiconductor chip and the inner end of the lead element, an enveloper sealing and encapsulating the plate-like mount, the semiconductor chip, the inner portion of the lead element, and the bonding-wire element.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: November 21, 2006
    Assignee: NEC Electronics Corporation
    Inventor: Takekazu Tanaka
  • Publication number: 20060170113
    Abstract: A technology providing an improvement in the durability in the condition of changing the temperature, while ensuring characteristics such as the applicability to applications utilizing larger electric current, lower resistance and the like can be achieved. A semiconductor device 100 includes a ceramic multiple-layered interconnect substrate 120, a silicon chip 110 that is flip-bonded to a chip-carrying region of the ceramic multiple-layered interconnect substrate 120, and an external connecting bumps 161 and an external connecting bumps 163, which are provided in the side that the silicon chip 110 of the ceramic multiple-layered interconnect substrate 120 is carried. The silicon chip 110 includes a front surface electrode and a back surface electrode.
    Type: Application
    Filed: January 19, 2006
    Publication date: August 3, 2006
    Inventors: Takekazu Tanaka, Ikuo Komatsu
  • Publication number: 20060001135
    Abstract: A package for an electronic component according to one embodiment of the invention has a chip mounting area mounting a semiconductor chip in a hollow part of a metal plate and a plurality of connection electrodes to be connected to a substrate. The plurality of connection electrodes are formed in opposite sides of the rectangular metal plate and arranged asymmetrically with respect to a perpendicular bisector of the opposite sides.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 5, 2006
    Applicant: NEC Electronics Corporation
    Inventor: Takekazu Tanaka
  • Publication number: 20050032271
    Abstract: A lead frame of the present invention includes a pair of base portions having a substantially flat bottom each. An island portion and electrode portions are partly connected to the tops of the base portions. The lead frame needs a minimum of production cost and promotes dense mounting of semiconductor devices to a circuit board.
    Type: Application
    Filed: September 9, 2004
    Publication date: February 10, 2005
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takekazu Tanaka
  • Publication number: 20050023658
    Abstract: A leadless type semiconductor package includes a plate-like mount, and at least one semiconductor chip mounted on the plate-like mount such that a bottom surface of the semiconductor chip is secured to the plate-like mount, and the semiconductor chip has at least one electrode pad formed on a top surface thereof. The package further includes at least one flat electrode electrically connected to the electrode pad, and a molded resin enveloper for completely sealing and encapsulating the semiconductor chip. The molded resin enveloper further partially seals and encapsulates the flat electrode such that a part of the flat electrode is exposed as an outer electrode pad on a top surface of the molded resin enveloper.
    Type: Application
    Filed: June 18, 2004
    Publication date: February 3, 2005
    Inventors: Yukinori Tabira, Takekazu Tanaka
  • Publication number: 20040082109
    Abstract: In a semiconductor package including at least one plate-like mount, a semiconductor chip has at least one electrode formed on a top surface thereof, and is mounted on the plate-like mount such that a bottom surface of the semiconductor chip is in contact with the plate-like mount. The semiconductor package also includes at least one lead element having an outer portion arranged to be flush with the plate-like mount, and an inner portion deformed and shaped to overhang the semiconductor chip such that an inner end of the lead element is spaced apart from the top surface of the semiconductor chip. The semiconductor package further includes a bonding-wire element bonded at ends thereof to the electrode of the semiconductor chip and the inner end of the lead element, an enveloper sealing and encapsulating the plate-like mount, the semiconductor chip, the inner portion of the lead element, and the bonding-wire element.
    Type: Application
    Filed: June 24, 2003
    Publication date: April 29, 2004
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Takekazu Tanaka
  • Publication number: 20020180011
    Abstract: A lead frame of the present invention includes a pair of base portions having a substantially flat bottom each. An island portion and electrode portions are partly connected to the tops of the base portions. The lead frame needs a minimum of production cost and promotes dense mounting of semiconductor devices to a circuit board.
    Type: Application
    Filed: May 30, 2002
    Publication date: December 5, 2002
    Applicant: NEC CORPORATION
    Inventor: Takekazu Tanaka