Abstract: An impact detection circuit includes a first detection section adapted to detect presence or absence of an impact input based on a first output signal as an output signal in a first detection axis of an inertial sensor having the first detection axis and a second detection axis different from each other, a second detection section adapted to detect presence or absence of an impact input based on a second output signal as an output signal in the second detection axis, and an impact detection determination section adapted to determine that an impact input has been made in a case in which both of the first detection section and the second detection section have detected the presence of the impact input.

Abstract: An oscillator includes an oscillation source, multiple temperature control elements, and a controller adapted to perform control to suppress an increase in current consumed in one or more of the temperature control elements during at least part of a period from when operation of the oscillation source initiates to when the oscillation source reaches a specified temperature.

Abstract: An oscillator includes an oscillation element, an oscillation circuit, a heat generation element, a temperature control circuit, and a temperature correction signal generation circuit adapted to generate a temperature correction signal used to correct a frequency-temperature characteristic. The temperature correction signal generation circuit includes a temperature sensor, a first-order correction signal generation circuit adapted to generate a first-order correction signal, and a high-order correction signal generation circuit adapted to generate a high-order correction signal.

Abstract: An oscillator includes a resonator; an oscillation circuit which oscillates the resonator; a D/A conversion circuit which receives digital data for controlling a frequency of the oscillation circuit; a first temperature sensor; and a temperature compensation circuit which is connected to the first temperature sensor. The oscillation circuit includes a first variable capacitor element and a second variable capacitor element. An output voltage of the D/A conversion circuit is applied to the first variable capacitor element. An output voltage of the temperature compensation circuit is applied to the second variable capacitor element.

Abstract: An oscillator includes an oscillation element, an oscillation circuit, a heat generation element, a temperature control circuit, and a temperature correction signal generation circuit adapted to generate a temperature correction signal used to correct a frequency-temperature characteristic. The temperature correction signal generation circuit includes a temperature sensor, a first-order correction signal generation circuit adapted to generate a first-order correction signal, and a high-order correction signal generation circuit adapted to generate a high-order correction signal.

Abstract: A physical quantity detecting circuit includes a detection signal generation section adapted to generate a detection signal corresponding to a physical quantity at a first rate based on an output signal of an inertial sensor, an arithmetic processing section adapted to perform arithmetic processing based on the detection signal, a measurement data holding section adapted to hold measurement data based on the detection signal, and a measurement completion flag generation section adapted to generate and then output a measurement completion flag at a second rate lower than the first rate.

Abstract: A physical quantity sensor includes a physical quantity sensor element and an IC connected to the physical quantity sensor element. The IC includes an analog power supply circuit that is switched to enable or disable, a signal processing unit to which a voltage is supplied from the analog power supply circuit and which processes a signal from the physical quantity sensor element, and a control circuit that sets the analog power supply circuit to enable within a processing period based on an external trigger and makes the signal processing unit process a physical quantity signal from the physical quantity sensor element intermittently for every processing period.

Abstract: A physical quantity detecting sensor includes a physical quantity detecting sensor element and an IC connected to the physical quantity detecting sensor element. The IC includes: a logic circuit; an analog circuit; a first regulator that supplies a logic power supply voltage generated based on a power supply voltage to the logic circuit; a second regulator that is switched to enable or disable and supplies an analog power supply voltage, which is generated based on the power supply voltage when the second regulator is set to enable, to the analog circuit; and a switch for supplying the logic power supply voltage to the analog circuit when the second regulator is set to disable.

Abstract: An impact detection circuit includes a first detection section adapted to detect presence or absence of an impact input based on a first output signal as an output signal in a first detection axis of an inertial sensor having the first detection axis and a second detection axis different from each other, a second detection section adapted to detect presence or absence of an impact input based on a second output signal as an output signal in the second detection axis, and an impact detection determination section adapted to determine that an impact input has been made in a case in which both of the first detection section and the second detection section have detected the presence of the impact input.

Abstract: A D/A conversion circuit includes a first D/A converting section which is connected with an output node, a first serial capacitor which is disposed between the output node and a first node, a second D/A converting section which is connected with the first node, and a control circuit. The first D/A converting section includes a first capacitor array section and a first switch array section. The second D/A converting section includes a second capacitor array section and a second switch array section. The control circuit performs a switch control for dynamically changing allocation of the capacitors to the respective bits of input digital data for the first switch array section of the first D/A converting section.

Abstract: An A/D conversion circuit in which a control circuit that has a successive approximation register storing data updated by a successive approximation operation generates correction data for correcting non-linearity between an input analog signal and an output digital signal, and a comparison unit corrects the non-linearity based on the correction data. An A/D conversion circuit includes a comparison unit which performs comparison operation in successive approximation and a control circuit having a successive approximation register storing successive approximation data updated by the successive approximation. The control circuit outputs correction data for correcting non-linearity between an input signal and output data of the A/D conversion circuit to the comparison unit based on one or plural bits of the successive approximation data. The comparison unit corrects the non-linearity of the A/D conversion circuit based on the correction data.

Abstract: A D/A conversion circuit includes a first D/A converting section which is connected with an output node, a first serial capacitor which is disposed between the output node and a first node, a second D/A converting section which is connected with the first node, and a control circuit. The first D/A converting section includes a first capacitor array section and a first switch array section. The second D/A converting section includes a second capacitor array section and a second switch array section. The control circuit performs a switch control for dynamically changing allocation of the capacitors to the respective bits of input digital data for the first switch array section of the first D/A converting section.

Abstract: An A/D conversion circuit in which a control circuit that has a successive approximation register storing data updated by a successive approximation operation generates correction data for correcting non-linearity between an input analog signal and an output digital signal, and a comparison unit corrects the non-linearity based on the correction data. An A/D conversion circuit includes a comparison unit which performs comparison operation in successive approximation and a control circuit having a successive approximation register storing successive approximation data updated by the successive approximation. The control circuit outputs correction data for correcting non-linearity between an input signal and output data of the A/D conversion circuit to the comparison unit based on one or plural bits of the successive approximation data. The comparison unit corrects the non-linearity of the A/D conversion circuit based on the correction data.

Abstract: A high-speed serial interface circuit includes a data receiver circuit, a clock signal receiver circuit, a logic circuit block that includes at least a serial/parallel conversion circuit, a free-running clock signal generation circuit, a clock signal detection circuit, and an output mask circuit. The clock signal detection circuit compares a received clock signal from the clock signal receiver circuit with a free-running clock signal from the free-running clock signal generation circuit to detect whether or not clock signals are transferred through differential clock signal lines. When the clock signal detection circuit has detected that the clock signals are not transferred through the differential clock signal lines, the output mask circuit masks an output signal from the logic circuit block so that the output signal is not transmitted to a circuit in the subsequent stage.

Abstract: An integrated circuit device includes a high-speed I/F circuit block which transfers data through a serial bus, and a driver logic circuit block which generates a display control signal. A first-conductivity-type transistor included in the high-speed I/F circuit block is formed in a second-conductivity-type well, and a second-conductivity-type transistor included in the high-speed I/F circuit block is formed in a first-conductivity-type well formed in a second-conductivity-type substrate to enclose the second-conductivity-type well. A first-conductivity-type transistor and a second-conductivity-type transistor included in the driver logic circuit block are formed in a region other than a region of the first-conductivity-type well for the high-speed interface circuit block.

Abstract: A high-speed serial interface circuit includes a data receiver circuit, a clock signal receiver circuit, a logic circuit block that includes at least a serial/parallel conversion circuit, a free-running clock signal generation circuit, a clock signal detection circuit, and an output mask circuit. The clock signal detection circuit compares a received clock signal from the clock signal receiver circuit with a free-running clock signal from the free-running clock signal generation circuit to detect whether or not clock signals are transferred through differential clock signal lines. When the clock signal detection circuit has detected that the clock signals are not transferred through the differential clock signal lines, the output mask circuit masks an output signal from the logic circuit block so that the output signal is not transmitted to a circuit in the subsequent stage.

Abstract: A high-speed serial interface circuit includes a data receiver circuit, a clock signal receiver circuit, a logic circuit block that includes at least a serial/parallel conversion circuit, a free-running clock signal generation circuit, a clock signal detection circuit, and an output mask circuit. The clock signal detection circuit compares a received clock signal from the clock signal receiver circuit with a free-running clock signal from the free-running clock signal generation circuit to detect whether or not clock signals are transferred through differential clock signal lines. When the clock signal detection circuit has detected that the clock signals are not transferred through the differential clock signal lines, the output mask circuit masks an output signal from the logic circuit block so that the output signal is not transmitted to a circuit in the subsequent stage.

Abstract: A high-speed serial interface circuit includes a data receiver circuit, a clock signal receiver circuit, a logic circuit block that includes at least a serial/parallel conversion circuit, a free-running clock signal generation circuit, a clock signal detection circuit, and an output mask circuit. The clock signal detection circuit compares a received clock signal from the clock signal receiver circuit with a free-running clock signal from the free-running clock signal generation circuit to detect whether or not clock signals are transferred through differential clock signal lines. When the clock signal detection circuit has detected that the clock signals are not transferred through the differential clock signal lines, the output mask circuit masks an output signal from the logic circuit block so that the output signal is not transmitted to a circuit in the subsequent stage.

Abstract: An integrated circuit device includes a high-speed I/F circuit block which transfers data through a serial bus, and a driver logic circuit block which generates a display control signal. The high-speed I/F circuit block includes a physical layer circuit including a receiver circuit, and a high-speed I/F logic circuit including a serial/parallel conversion circuit. The high-speed I/F circuit block is disposed so that the high-speed I/F logic circuit is disposed between the physical layer circuit and the driver logic circuit block and the physical layer circuit and the driver logic circuit block are not adjacently disposed.

Abstract: An integrated circuit device includes a high-speed I/F circuit block which transfers data through a serial bus, and a driver logic circuit block which generates a display control signal. The high-speed I/F circuit block includes a physical layer circuit including a receiver circuit, and a high-speed I/F logic circuit including a serial/parallel conversion circuit. The high-speed I/F circuit block is disposed so that the high-speed I/F logic circuit is disposed between the physical layer circuit and the driver logic circuit block and the physical layer circuit and the driver logic circuit block are not adjacently disposed.