Patents by Inventor Takemi Yonezawa

Takemi Yonezawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070045659
    Abstract: An integrated circuit device includes a high-speed I/F circuit block which transfers data through a serial bus, and a driver logic circuit block which generates a display control signal. A first-conductivity-type transistor included in the high-speed I/F circuit block is formed in a second-conductivity-type well, and a second-conductivity-type transistor included in the high-speed I/F circuit block is formed in a first-conductivity-type well formed in a second-conductivity-type substrate to enclose the second-conductivity-type well. A first-conductivity-type transistor and a second-conductivity-type transistor included in the driver logic circuit block are formed in a region other than a region of the first-conductivity-type well for the high-speed interface circuit block.
    Type: Application
    Filed: August 30, 2006
    Publication date: March 1, 2007
    Inventors: Masaaki Abe, Hidehiko Yajima, Takemi Yonezawa, Fumikazu Komatsu, Mitsuaki Sawada
  • Patent number: 7173458
    Abstract: A semiconductor device includes a differential signal output circuit that outputs a differential signal, an amplitude control signal generation circuit that generates an amplitude control signal to control an amplitude of the differential signal for the differential signal output circuit, and a center voltage level control signal generation circuit that generates a center voltage level control signal to control a center voltage level of the differential signal. The differential signal output circuit outputs the differential signal having the center voltage level based on the center voltage level control signal and an output level based on the amplitude control signal. A forming region of the center voltage level control signal generation circuit and a forming region of the differential signal output circuit are provided near each other on a semiconductor substrate where operation characteristics of transistors formed respectively in the two forming regions become equal.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: February 6, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Takemi Yonezawa
  • Publication number: 20050104649
    Abstract: A differential signal output circuit is provided in a semiconductor chip, wherein resistances are inserted between a pair of output terminals of a pair of signal lines and pads to be connected to the respective output terminals. The resistances are provided inside the semiconductor chip. In particular, the resistance components are inserted between the inductance components of bonding wires and lead frames and capacitance components such as wiring capacitances.
    Type: Application
    Filed: September 9, 2004
    Publication date: May 19, 2005
    Inventor: Takemi Yonezawa
  • Publication number: 20050083102
    Abstract: A semiconductor device includes a differential signal output circuit that outputs a differential signal, an amplitude control signal generation circuit that generates an amplitude control signal to control an amplitude of the differential signal for the differential signal output circuit, and a center voltage level control signal generation circuit that generates a center voltage level control signal to control a center voltage level of the differential signal. The differential signal output circuit outputs the differential signal having the center voltage level based on the center voltage level control signal and an output level based on the amplitude control signal. A forming region of the center voltage level control signal generation circuit and a forming region of the differential signal output circuit are provided near each other on a semiconductor substrate where operation characteristics of transistors formed respectively in the two forming regions become equal.
    Type: Application
    Filed: September 2, 2004
    Publication date: April 21, 2005
    Inventor: Takemi Yonezawa
  • Patent number: 6456532
    Abstract: The present invention is intended to provide a semiconductor memory circuit that can store analog and many-valued data at high speed and with a high degree of accuracy.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: September 24, 2002
    Assignees: Tadahiro Ohmi, Tadashi Shibata, UCT Corporation, I & F Inc.
    Inventors: Tadahiro Ohmi, Tadashi Shibata, Keng Hoong Wee, Takemi Yonezawa, Toshiyuki Nozawa, Takahisa Nitta