Abstract: A compiler apparatus is capable of generating instruction sequences causing a processor to operate with lower power consumption. The compiler apparatus translates a source program into a machine language program for a processor including execution units which can execute instructions in parallel, and including instruction issue units which issue the instructions executed, respectively, by the execution units. The compiler apparatus includes a parser unit operable to parse the source program, an intermediate code conversion unit operable to convert the parsed source program into intermediate codes, an optimization unit operable to optimize the intermediate codes to reduce a hamming distance between instructions from the same instruction issue unit in consecutive instruction cycles, and includes a code generation unit operable to convert the optimized intermediate codes into machine language instructions.

Abstract: An instruction conversion apparatus for optimizing an instruction program formed of a plurality of instructions to be suitable for execution by a microprocessor that has a plurality of hard ware resources. The apparatus includes a power control information analysis unit for detecting a power controllable hardware resource that does not operate for a certain specific instruction region in the instruction program while the microprocessor is at work, and a power control instruction providing unit for providing the instruction program with an instruction regarding the power control based on the result of the detection made by the power control information analysis unit.

Abstract: An instruction conversion apparatus for optimizing an instruction program formed of a plurality of instructions to be suitable for execution by a microprocessor that has a plurality of hard ware resources. The apparatus includes a power control information analysis unit for detecting a power controllable hardware resource that does not operate for a certain specific instruction region in the instruction program while the microprocessor is at work, and a power control instruction providing unit for providing the instruction program with an instruction regarding the power control based on the result of the detection made by the power control information analysis unit.

Abstract: The state control device for controlling an internal state of information processing equipment includes a scenario table, an information recorder, an information player and a state change controller. The information recorder acquires sync information and one item or a plurality of items of state information from the information processing equipment and records the acquired sync information and state information in association with each other in the scenario table. The information player, receiving sync information from the information processing equipment, acquires state information associated with sync information corresponding to the received sync information, among the sync information stored in the scenario table, from the scenario table, and supplies the acquired state information to the state change controller. The state change controller controls the inside of the information processing equipment based on the state information received from the information player.

Abstract: The microprocessor is provided with a program modification function not attended with unnecessary branch instructions or interrupt processes. The instruction storage unit includes read-only-memory (ROM) for storing instructions composing a program to be processed and a modified instruction storage unit for storing modified instructions for program modification. When the upper bits of an instruction address supplied from the program counter match with the upper bits of the modifying address, the address translation unit translates the upper bits of the instruction address into the upper bits of the substitutive address where the modified instruction is stored in the modified instruction storage unit.

Abstract: A processor has: a power table including a plurality of power control registers each rewritably storing power control information; a condition determiner for rewritably storing a plurality of operating conditions (e.g., a comparison address to be compared with the program counter) and determining which one of the plurality of operating conditions is satisfied by a current operation of the processor so as to supply an index signal to select one of the plurality of power control registers based on the determination; and a voltage/clock controller for controlling the power consumption in a control object circuit block according to the power control information in one of the power control registers that is selected by the index signal.

Abstract: In a microprocessor for executing an instruction program into which a power control instruction has been automatically inserted, an occurrence of a problem (bugs) which is caused by automatically inserting the power control instruction is prevented, while the power control instruction designates power control operations for individually controlling electric power with respect to operation resources of the microprocessor. Also, when the problems happen to occur, a problem which is caused by writing the instruction program can be discriminated from another problem which is caused by an instruction which is automatically inserted by a compiler.

Abstract: A processor has: a power table including a plurality of power control registers each rewritably storing power control information; a condition determiner for rewritably storing a plurality of operating conditions (e.g., a comparison address to be compared with the program counter) and determining which one of the plurality of operating conditions is satisfied by a current operation of the processor so as to supply an index signal to select one of the plurality of power control registers based on the determination; and a voltage/clock controller for controlling the power consumption in a control object circuit block according to the power control information in one of the power control registers that is selected by the index signal.

Abstract: A compiler apparatus that is capable of generating instruction sequences for causing a processor with parallel processing capability to operate with lower power consumption is a compiler apparatus that translates a source program into a machine language program for the processor including a plurality of execution units which can execute instructions in parallel and a plurality of instruction issue units which issue the instructions executed respectively by the plurality of execution units, and includes: a parser unit operable to parse the source program; an intermediate code conversion unit operable to convert the parsed source program into intermediate codes; an optimization unit operable to optimize the intermediate codes so as to reduce a hamming distance between instructions placed in positions corresponding to the same instruction issue unit in consecutive instruction cycles, without changing dependency between the instructions corresponding to the intermediate codes; and a code generation unit operable

Abstract: An instruction conversion apparatus for optimizing an instruction program formed of a plurality of instructions to be suitable for execution by a microprocessor that has a plurality of hard ware resources. The apparatus includes a power control information analysis unit for detecting a power controllable hardware resource that does not operate for a certain specific instruction region in the instruction program while the microprocessor is at work, and a power control instruction providing unit for providing the instruction program with an instruction regarding the power control based on the result of the detection made by the power control information analysis unit.

Abstract: A processor has: a power table including a plurality of power control registers each rewritably storing power control information; a condition determiner for rewritably storing a plurality of operating conditions (e.g., a comparison address to be compared with the program counter) and determining which one of the plurality of operating conditions is satisfied by a current operation of the processor so as to supply an index signal to select one of the plurality of power control registers based on the determination; and a voltage/clock controller for controlling the power consumption in a control object circuit block according to the power control information in one of the power control registers that is selected by the index signal.