Patents by Inventor Takeo Fujii
Takeo Fujii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100232436Abstract: The degradation of the communication characteristics and the throughput of the entire network can be improved. The failures of sending and receiving are reduced and the transmission time is reduced. In a multi-hop communication method how the source terminal 11 transmits and receives the packets with destination terminal 12 through at least one relay terminal 13, the relay terminal 13 and/or the destination terminal 12 includes a table TBL of use channel candidates that is issued by the source terminal 11, and the relay terminal 13 and/or the destination terminal 12 selects a use channel for sending the data packets from the channel candidates registered in the table and sends the data packets.Type: ApplicationFiled: January 30, 2007Publication date: September 16, 2010Applicant: THE UNIVERSITY OF ELECTRO-COMMUNICATIONSInventors: Takeo Fujii, Hiromasa Uchiyama
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Publication number: 20080165721Abstract: This invention provides a communication system, a repeater terminal in the communication system and a communication method for improving the characteristics in a multi-hop communication by a diversity gain and reduces the power consumption by wasteful retransmission in packet transmission at a wireless terminal. When a transmitter terminal S sends a packet first time, repeater terminals R1-R13 perform a data transmission by retransmission at all the terminals which received the packet. When a transmitter terminal S sends a packet second time, a repeater terminal determines its own contribution based on the hop numbers of the repeating in the packet transmission and the return ACK (or NACK) repeating. The repeater terminal with a high contribution autonomously determines to be in “repeater mode” and the repeater terminal with a low contribution autonomously determines to be in “sleep mode”.Type: ApplicationFiled: January 20, 2006Publication date: July 10, 2008Applicant: NATIONAL UNIVERSITY CORPORATIOI TOKYO UNVERSITY OF AGRICULTURE AND TECHNOLOGYInventors: Takeo Fujii, Erina Kojima
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Publication number: 20030127351Abstract: There is developed a label which enables purchasers or ordinary consumers to identify suitable commodity products at a glance, thereby providing facilities for consumers when they purchase commodity products. A target user information label section corresponding to a target user of paper diapers packed in a package is printed at a position conspicuous for ordinary consumers on the surface of the package, along with a tradename of the paper diapers. All target user designs corresponding to all target users of paper diapers to be handled as commodities are displayed as a single set in the information label section. A specific target user design corresponding to a target user of the paper diapers packed in the package is displayed greater in size than the other target user designs belonging to the set.Type: ApplicationFiled: February 21, 2003Publication date: July 10, 2003Inventors: Tsuyoshi Takahashi, Yuko Fukui, Takeo Fujii, Nobuko Uchibori
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Patent number: 6568530Abstract: There is developed a label which enables purchasers or ordinary consumers to identify suitable commodity products at a glance, thereby providing facilities for consumers when they purchase commodity products. A target user information label section corresponding to a target user of paper diapers packed in a package is printed at a position conspicuous for ordinary consumers on the surface of the package, along with a tradename of the paper diapers. All target user designs corresponding to all target users of paper diapers to be handled as commodities are displayed as a single set in the information label section. A specific target user design corresponding to a target user of the paper diapers packed in the package is displayed greater in size than the other target user designs belonging to the set.Type: GrantFiled: May 1, 2001Date of Patent: May 27, 2003Assignee: Uni-Charm CorporationInventors: Tsuyoshi Takahashi, Yuko Fukui, Takeo Fujii, Nobuko Uchibori
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Patent number: 6537882Abstract: The present invention relates to a semiconductor device comprising a first MISFET group and a second MISFET group each formed on a semiconductor substrate. Upon fabrication of it, an MOSFET constituting a memory cell and an MOSFET constituting a peripheral circuit are not formed in the same step. When a side wall is formed on each side of a gate electrode of the MOSFET constituting the peripheral circuit, the memory cell region is covered and protected with a layer which is to be a gate electrode. The semiconductor device thus fabricated has no side walls in the MOSFET constituting a memory cell. According to the present invention, a semiconductor device of high reliability can be fabricated by forming one MOSFET free of side walls. Upon fabrication, it is possible to easily control the size or etching of the device, thereby widening the fabrication range.Type: GrantFiled: August 15, 1997Date of Patent: March 25, 2003Assignees: NEC Corporation, NEC Electronic CorporationInventor: Takeo Fujii
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Publication number: 20020088732Abstract: There is developed a label which enables purchasers or ordinary consumers to identify suitable commodity products at a glance, thereby providing facilities for consumers when they purchase commodity products. A target user information label section corresponding to a target user of paper diapers packed in a package is printed at a position conspicuous for ordinary consumers on the surface of the package, along with a tradename of the paper diapers. All target user designs corresponding to all target users of paper diapers to be handled as commodities are displayed as a single set in the information label section. A specific target user design corresponding to a target user of the paper diapers packed in the package is displayed greater in size than the other target user designs belonging to the set.Type: ApplicationFiled: May 1, 2001Publication date: July 11, 2002Inventors: Tsuyoshi Takahashi, Yuko Fukui, Takeo Fujii, Nobuko Uchibori
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Patent number: 6367912Abstract: An ink jet recording apparatus is provided with a black head and a plurality of color heads. The black head has a predetermined number of first orifices aligned at predetermined intervals (e.g. 0.0169 mm) in a sub scanning direction (direction in which a print medium travels). The plurality of color heads eject different colored ink drops. Each color head has the predetermined number of second orifices aligned in the sub scanning direction perpendicular to the main scanning direction. The second orifices of adjacent color heads are aligned in a main scanning direction perpendicular to the sub scanning direction.Type: GrantFiled: October 23, 1998Date of Patent: April 9, 2002Assignee: Oki Data CorporationInventors: Mitsuru Kishimoto, Hideyuki Kobayashi, Noboru Ooishi, Kiyoshi Ikeda, Takeo Fujii, Hiroyuki Ueki, Masahiko Shimosugi, Shigenori Koido
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Patent number: 6335873Abstract: A semiconductor integrated circuit device is configured using a DRAM and an SRAM between which data transfer is performed by way of a data transfer circuit using data transfer bus lines. Herein, the DRAM is divided into at least two DRAM arrays, each of which contains a number of columns each consisting of memory cells. In addition, the columns are arranged in mixture in connection with external I/O terminals respectively in such a way that columns respectively containing memory cells which are simultaneously subjected to read operations within a same cycle are arranged not to adjoin each other. Thus, it is possible to reduce a probability in which multiple memory cells which are simultaneously subjected to read operations within the same cycle exist within a range of an area under influence of charged particles, which are produced locally due to neutrons.Type: GrantFiled: March 14, 2000Date of Patent: January 1, 2002Assignee: NEC CorporationInventors: Masaki Kawaguchi, Takeo Fujii, Yoshinori Matsui, Hiroshi Furuta, Seiichi Hannai
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Patent number: 6275367Abstract: In a semiconductor circuit device, an internal circuit, a common wiring pattern, a plurality of external terminals including a ground terminal, and a plurality of protection elements is provided. Each of the plurality of protection elements is connected to one of the plurality of external terminals and the common wiring pattern. Each protection element includes a clamp circuit. The clamp circuit of each of the plurality of protection elements respectively connected to the plurality of external terminals other than the ground terminal has a clamp voltage higher than a power supply voltage supplied to the internal circuit. On the other hand, the clamp circuit of the protection element connected to the ground terminal as a ground terminal clamp circuit has a clamp voltage lower than those of the clamp circuits other than the ground terminal clamp circuit.Type: GrantFiled: June 1, 1999Date of Patent: August 14, 2001Assignee: NEC CorporationInventors: Kaoru Narita, Takeo Fujii
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Publication number: 20010012688Abstract: In order to form a node contact hole in an inter-level insulating structure between bit lines spaced by the minimum length defined in design rules, a preliminary node contact hole is firstly formed in the inter-level insulating structure between the bit lines in such a manner as to have a length greater than the minimum length, and an insulating side wall spacer is formed on the inner surface defining the preliminary node contact hole so as to form the node contact hole having a length less than the minimum length, thereby forming a quite narrow node contact hole without a short-circuit between the bit lines and a storage node electrode.Type: ApplicationFiled: September 25, 1998Publication date: August 9, 2001Inventors: MASAKI KAWAGUCHI, TAKEO FUJII
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Patent number: 6191633Abstract: A Semiconductor integrated circuit with a protection circuit against electrostatic discharge. A clamping element is connected with MIS transistor to prevent the breakdown under the charged device model. A parasitic bipolar transistor, a MOS transistor or MIS transistor whose gate is composed of an insulating film thicker than that of the transfer gate, can be used as the clamping element.Type: GrantFiled: September 9, 1998Date of Patent: February 20, 2001Assignee: NEC CorporationInventors: Takeo Fujii, Kaoru Narita, Yoko Horiguchi
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Patent number: 6175139Abstract: A semiconductor device includes a metal terminal provided on a semiconductor substrate and a protection element. The protection element includes an insulated gate field-effect transistor. The transistor has a first diffusion layer of a reverse conductive-type formed on one conductive type region of the semiconductor substrate and connected to the metal terminal, as its source. The transistor also includes a second diffusion layer of a reverse conductive-type connected to an electrode wire having a constant electric potential, as its source, and has a gate electrode connected to the electrode wire. A lateral bipolar transistor includes a third diffusion layer of a reverse conductive-type formed with a constant spaced distance with respect to the second diffusion layer and connected to the metal terminal, as its collector, and also has the second diffusion layer as its emitter, and furthermore has the one conductive-type region as its base.Type: GrantFiled: November 17, 1998Date of Patent: January 16, 2001Assignee: NEC CorporationInventors: Yoko Horiguchi, Kaoru Narita, Takeo Fujii
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Patent number: 6101078Abstract: A lead on chip (LOC) semiconductor device or a chip on lead (COL) semiconductor device with a protection circuit. Non-connection pins are made shorter than connection pins to reduce the inductance of the non-connection pins, or to obtain a different capability of the protection circuit for non-connection pins with respect to connection pins. The time constant of the protection circuit for the non-connection pins is made longer than that of the protection circuit for the connection pins. Further, the clamping capability for the connection pins is made greater than that for another connection pin adjacent to the connection pin.Type: GrantFiled: September 9, 1998Date of Patent: August 8, 2000Assignee: NEC CorporationInventors: Takeo Fujii, Kaoru Narita, Yoko Horiguchi
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Patent number: 5980030Abstract: A recording apparatus has a print head with an ink tank for supplying ink to the print head. The ink tank is carried together with a print head on a carriage, which is moved over a print medium so that the print head prints data on the print medium. The ink tank has an ink-empty sensor which outputs a first signal upon detecting that the ink in the ink tank has decreased to a lower limit. A controller causes the carriage to move to an ink-refilling position in response to the first signal. Then, the controller causes an ink-refilling mechanism to refill the ink tank with ink from an ink reservoir located above the ink tank. The ink tank also has an ink-full sensor which outputs a second signal upon detecting that the ink in the ink tank has increased to an upper limit. The ink-refilling mechanism stops an ink-refilling operation in response to the second signal. A timer may be used in place of the ink-full sensor.Type: GrantFiled: July 17, 1996Date of Patent: November 9, 1999Assignee: Oki Data CorporationInventor: Takeo Fujii
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Patent number: 5973901Abstract: In a semiconductor circuit device, an internal circuit, a common wiring pattern, a plurality of external terminals including a ground terminal, and a plurality of protection elements is provided. Each of the plurality of protection elements is connected to one of the plurality of external terminals and the common wiring pattern. Each protection element includes a clamp circuit. The clamp circuit of each of the plurality of protection elements respectively connected to the plurality of external terminals other than the ground terminal has a clamp voltage higher than a power supply voltage supplied to the internal circuit. On the other hand, the clamp circuit of the protection element connected to the ground terminal as a ground terminal clamp circuit has a clamp voltage lower than those of the clamp circuits other than the ground terminal clamp circuit.Type: GrantFiled: August 1, 1997Date of Patent: October 26, 1999Assignee: NEC CorporationInventors: Kaoru Narita, Takeo Fujii
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Patent number: 5936283Abstract: According to the present invention, a MOSFET for an input/output protective circuit in which a source diffusion layer, a drain diffusion layer and a gate electrode are formed on a semiconductor substrate comprises a high melting point metal silicide layer disposed on the drain diffusion layer through a first insulating film, a metal wire layer disposed on the high melting point metal silicide layer through a second insulating film, at least two first contact holes for electrically connecting the high melting point metal silicide layer and the metal wire layer, and a second contact hole for electrically connecting the high melting point metal silicide layer and the drain diffusion layer, wherein the second contact hole is disposed at a substantial center between the two first contact holes.Type: GrantFiled: August 5, 1997Date of Patent: August 10, 1999Assignee: NEC CorporationInventors: Kaoru Narita, Takeo Fujii
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Patent number: 5910675Abstract: A semiconductor device includes a metal terminal provided on a semiconductor substrate and a protection element. The protection element includes an insulated gate field-effect transistor. The transistor has a first diffusion layer of a reverse conductive-type formed on one conductive type region of the semiconductor substrate and connected to the metal terminal, as its source. The transistor also includes a second diffusion layer of a reverse conductive-type connected to an electrode wire having a constant electric potential, as its source, and has a gate electrode connected to the electrode wire. A lateral bipolar transistor includes a third diffusion layer of a reverse conductive-type formed with a constant spaced distance with respect to the second diffusion layer and connected to the metal terminal, as its collector, and also has the second diffusion layer as its emitter, and furthermore has the one conductive-type region as its base.Type: GrantFiled: December 11, 1996Date of Patent: June 8, 1999Assignee: NEC CorporationInventors: Yoko Horiguchi, Kaoru Narita, Takeo Fujii
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Patent number: 5274598Abstract: A semiconductor memory provided with improved sense amplifier-bit line arrangement which is suitable for a high-speed and high-sensitivity read operation. The memory comprises a main bit line pair, a main sense amplifier, a plurality of sub-bit line pairs and a plurality of sub-sense amplifiers in each column. Each of the sub-sense amplifiers includes a pair of output nodes coupled to the main bit line pair and a pair of input nodes coupled to one of the sub-bit line pairs. A pair of switch elements are inserted between the main bit line pair and each one of the sub-bit line pairs for selectively feeding an output of the main sense amplifier back to one of the sub-bit line pair selected.Type: GrantFiled: June 17, 1991Date of Patent: December 28, 1993Assignee: NEC CorporationInventors: Takeo Fujii, Toshio Komuro
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Patent number: 5256822Abstract: There is disclosed an imine derivative of the general formula: ##STR1## wherein R.sup.1 and R.sup.2 are the same or different and are hydrogen, C.sub.1 -C.sub.6 alkyl or aryl, with the proviso that R.sup.1 and R.sup.2 are not simultaneously hydrogen; or R.sup.1 and R.sup.2 are joined together to form C.sub.4 -C.sub.6 alkylene. Also disclosed is a process for the production of the imine derivative.Type: GrantFiled: February 5, 1993Date of Patent: October 26, 1993Assignee: Sumitomo Chemical Company, LimitedInventors: Ichiki Takemoto, Takeo Fujii, Hideyuki Goto, Ritsu Okajima
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Patent number: 5187549Abstract: For decreasing the amount of real estate assigned to each memory cell, a random access memory device is fabricated on a semiconductor substrate from a plurality of memory cells each comprising a switching transistor and a storage capacitor, wherein the storage capacitor comprises a lower electrode provided over one of the source and drain regions of the switching transistor and held in contact therewith, a dielectric film structure covering the lower electrode, and an upper electrode held in contact with the dielectric film structure and having at least one side edge substantially self-aligned with one side edge of the lower electrode without any tolerance.Type: GrantFiled: February 5, 1991Date of Patent: February 16, 1993Assignee: NEC CorporationInventor: Takeo Fujii