Patents by Inventor Takeo Katoh
Takeo Katoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10177008Abstract: This method for manufacturing a silicon wafer includes: a first heat treatment step of performing RTP treatment on the silicon wafer in an oxidizing atmosphere; a step of removing a region in the silicon wafer in which an oxygen concentration increases in the first heat treatment step; a second heat treatment step of performing, after performing this removing step, RTP treatment on the silicon wafer in a nitriding atmosphere or an Ar atmosphere; and a step of removing, after performing the second heat treatment step, a region in the silicon wafer in which an oxygen concentration decreases in the second heat treatment step. This method enables the manufacture of a silicon wafer in which latent defects such as OSF nuclei and oxygen precipitate nuclei existing in a PV region are destroyed or reduced, and that has a gettering site.Type: GrantFiled: January 14, 2014Date of Patent: January 8, 2019Assignee: SUMCO CORPORATIONInventors: Takashi Nakayama, Takeo Katoh, Kazumi Tanabe, Shigeru Umeno
-
Publication number: 20160322233Abstract: This method for manufacturing a silicon wafer includes: a first heat treatment step of performing RTP treatment on the silicon wafer in an oxidizing atmosphere; a step of removing a region in the silicon wafer in which an oxygen concentration increases in the first heat treatment step; a second heat treatment step of performing, after performing this removing step, RTP treatment on the silicon wafer in a nitriding atmosphere or an Ar atmosphere; and a step of removing, after performing the second heat treatment step, a region in the silicon wafer in which an oxygen concentration decreases in the second heat treatment step. This method enables the manufacture of a silicon wafer in which latent defects such as OSF nuclei and oxygen precipitate nuclei existing in a PV region are destroyed or reduced, and that has a gettering site.Type: ApplicationFiled: January 14, 2014Publication date: November 3, 2016Applicant: SUMCO CORPORATIONInventors: Takashi NAKAYAMA, Takeo KATOH, Kazumi TANABE, Shigeru UMENO
-
Patent number: 8877643Abstract: This invention is to provide a method of polishing a silicon wafer wherein a high flatness can be attained likewise the conventional polishing method and further the occurrence of defects due to the remaining of substances included in the polishing solution on the surface of the wafer can be suppressed as well as a polished silicon wafer. The method of polishing a silicon wafer by supplying a polishing solution containing abrasive grains onto a surface of a polishing pad and then relatively sliding the polishing pad to a silicon wafer to polish the surface of the silicon wafer, is characterized in that the number of abrasive grains included in the polishing solution is controlled to not more than 5×1013 grains/cm3.Type: GrantFiled: May 28, 2010Date of Patent: November 4, 2014Assignee: Sumco CorporationInventors: Shuhei Matsuda, Tetsuro Iwashita, Ryuichi Tanimoto, Takeru Takushima, Takeo Katoh
-
Patent number: 8759229Abstract: A method for manufacturing an epitaxial wafer that can reduce occurrence of a surface defect or a slip formed on an epitaxial layer is provided. The manufacturing method is characterized by comprising: a smoothing step of controlling application of an etchant to a wafer surface in accordance with a surface shape of a silicon wafer to smooth the wafer surface; and an epitaxial layer forming step of forming an epitaxial layer formed of a silicon single crystal on the surface of the wafer based on epitaxial growth.Type: GrantFiled: January 24, 2007Date of Patent: June 24, 2014Assignee: Sumco CorporationInventors: Sakae Koyata, Kazushige Takaishi, Tomohiro Hashii, Katsuhiko Murayama, Takeo Katoh
-
Patent number: 8466071Abstract: An object of the present invention is to provide a method for etching a single wafer, which effectively realizes a high flatness of wafer and an increase in productivity thereof. In a method for etching a single wafer, a single thin disk-like wafer sliced from a silicon single crystal ingot is spun, and a front surface of the wafer is etched with an etching solution supplied thereto. In the method, a plurality of supply nozzles are disposed above and opposite to the front surface of the wafer at different portions in the radial direction of the wafer, respectively; and then one or more conditions selected from the group consisting of temperatures, kinds, and supply flow rates of etching solutions from the plurality of supply nozzles are changed.Type: GrantFiled: January 24, 2007Date of Patent: June 18, 2013Assignee: Sumco CorporationInventors: Sakae Koyata, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh
-
Patent number: 8379196Abstract: A semiconductor wafer whose number of LPDs per wafer is equal to or smaller than a predetermined number is sorted out, and a judgment as to whether a semiconductor wafer is a non-defective wafer is made visually based on a haze map of the semiconductor wafer subjected to the sorting. Moreover, a semiconductor wafer whose number of LPDs per wafer is equal to or smaller than a predetermined number is sorted out. Then, from the semiconductor wafers subjected to the sorting, a semiconductor wafer whose in-plane standard deviation and in-plane average value of the haze signals in a wafer plane have a specific relationship is sorted out, and this semiconductor wafer is judged to be a non-defective wafer. In this way, a method for judging whether a semiconductor wafer is a non-defective wafer or a defective wafer, the method that can make a judgment more uniform and accurate without dependence on the difference in the S/N ratio between inspection apparatuses using a laser scattering method, is provided.Type: GrantFiled: June 2, 2010Date of Patent: February 19, 2013Assignee: Sumco CorporationInventors: Eiji Kamiyama, Takashi Nakayama, Takeo Katoh
-
Publication number: 20120080775Abstract: This invention is to provide a method of polishing a silicon wafer wherein a high flatness can be attained likewise the conventional polishing method and further the occurrence of defects due to the remaining of substances included in the polishing solution on the surface of the wafer can be suppressed as well as a polished silicon wafer. The method of polishing a silicon wafer by supplying a polishing solution containing abrasive grains onto a surface of a polishing pad and then relatively sliding the polishing pad to a silicon wafer to polish the surface of the silicon wafer, is characterized in that the number of abrasive grains included in the polishing solution is controlled to not more than 5×1013 grains/cm3.Type: ApplicationFiled: May 28, 2010Publication date: April 5, 2012Inventors: Shuhei Matsuda, Tetsuro Iwashita, Ryuichi Tanimoto, Takeru Takushima, Takeo Katoh
-
Patent number: 8147295Abstract: A silicon wafer is polished by applying a polishing solution substantially containing no abrasive grain onto a surface of a polishing pad having a given fixed grain bonded abrasive and then relatively sliding the polishing pad to a silicon wafer to polish the surface of the silicon wafer, wherein a hydroplane layer is formed by the polishing solution supplied between the surface of the silicon wafer and the surface of the polishing pad and a thickness of the hydroplane layer is controlled to change a polishing state of the surface of the silicon wafer.Type: GrantFiled: May 27, 2009Date of Patent: April 3, 2012Assignee: Sumco CorporationInventors: Takeo Katoh, Ryuichi Tanimoto, Shinichi Ogata, Takeru Takushima, Kazushige Takaishi
-
Patent number: 8066896Abstract: An apparatus for etching a wafer by a single-wafer process comprises a fluid supplying device which feeds an etching fluid on a wafer, and a wafer-chuck for horizontally holding the wafer. The wafer-chuck is equipped with a gas injection device for injecting a gas to the wafer, a first fluid-aspirating device, and a second fluid-aspirating device. The etching fluid supplied on the wafer is spread by a rotation of the wafer. The etching fluid is scattered by a centrifugal force, or flows down over an edge portion of the wafer and is blown-off by the gas injected from the gas injection unit, and is aspirated by the first fluid-aspirating device or the second fluid-aspirating device.Type: GrantFiled: August 15, 2007Date of Patent: November 29, 2011Assignee: Sumco CorporationInventors: Sakae Koyata, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh
-
Patent number: 7955982Abstract: Disclosed is a method for smoothing the surface of at least one side of a wafer which is obtained by slicing a semiconductor ingot. In this method, a fluid is applied according to projections of the wafer surface, thereby reducing the projections. Alternatively, a fluid is applied over the wafer surface, thereby smoothing the entire surface of the wafer while reducing the projections in the wafer surface.Type: GrantFiled: January 17, 2007Date of Patent: June 7, 2011Assignee: Sumco CorporationInventors: Takeo Katoh, Tomohiro Hashii, Katsuhiko Murayama, Sakae Koyata, Kazushige Takaishi
-
Patent number: 7906438Abstract: An object of the present invention is to provide a single wafer etching apparatus realizing a high flatness of wafers and an increase in productivity thereof. In the single wafer etching apparatus, a single thin disk-like wafer sliced from a silicon single crystal ingot is mounted on a wafer chuck and spun thereon, and an overall front surface of the wafer is etched with an etching solution supplied thereto by centrifugal force generated by spinning the wafer 11. The singe wafer etching apparatus includes a plurality of supply nozzles 26, 27 capable of discharging the etching solution 14 from discharge openings 26a, 27a onto the front surface of the wafer 11, nozzle-moving devices each capable of independently moving the plurality of supply nozzles 28, 29, and an etching solution supplying device 30 for supplying the etching solution 14 to each of the plurality of supply nozzles and discharging the etching solution 14 from each of the discharge openings to the front surface of the wafer 11.Type: GrantFiled: January 31, 2007Date of Patent: March 15, 2011Assignee: Sumco CorporationInventors: Sakae Koyata, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh
-
Publication number: 20100309461Abstract: A semiconductor wafer whose number of LPDs per wafer is equal to or smaller than a predetermined number is sorted out, and a judgment as to whether a semiconductor wafer is a non-defective wafer is made visually based on a haze map of the semiconductor wafer subjected to the sorting. Moreover, a semiconductor wafer whose number of LPDs per wafer is equal to or smaller than a predetermined number is sorted out. Then, from the semiconductor wafers subjected to the sorting, a semiconductor wafer whose in-plane standard deviation and in-plane average value of the haze signals in a wafer plane have a specific relationship is sorted out, and this semiconductor wafer is judged to be a non-defective wafer. In this way, a method for judging whether a semiconductor wafer is a non-defective wafer or a defective wafer, the method that can make a judgment more uniform and accurate without dependence on the difference in the S/N ratio between inspection apparatuses using a laser scattering method, is provided.Type: ApplicationFiled: June 2, 2010Publication date: December 9, 2010Applicant: SUMCO CORPORATIONInventors: Eiji Kamiyama, Takashi Nakayama, Takeo Katoh
-
Patent number: 7833908Abstract: A slurry composition for chemical-mechanical polishing capable of compensating nanotopography effect present on the surface of a wafer, and a method for planarizing the surface of a semiconductor device that utilizes the same are disclosed. The slurry composition of the present invention is aimed at compensating the nanotopography effect during chemical mechanical polishing process of the oxide layer formed on the surface of the wafer, and contains abrasive particles and an additive, wherein the size of the abrasive particles and the concentration of the additive are controlled within predetermined ranges in order to control the deviation of thickness (OTD) of the oxide layer below a certain level after the chemical mechanical polishing process.Type: GrantFiled: May 11, 2004Date of Patent: November 16, 2010Assignees: Sumco Corporation, Hanyang Hak Won Co.Inventors: Jea Gun Park, Takeo Katoh, Won Mo Lee, Hyun Goo Kang, Sung Jun Kim, Un Gyu Paik
-
Publication number: 20100151597Abstract: Disclosed is a method for smoothing the surface of at least one side of a wafer which is obtained by slicing a semiconductor ingot. In this method, a fluid is applied according to projections of the wafer surface, thereby reducing the projections. Alternatively, a fluid is applied over the wafer surface, thereby smoothing the entire surface of the wafer while reducing the projections in the wafer surface.Type: ApplicationFiled: January 17, 2007Publication date: June 17, 2010Applicant: SUMCO CORPORATIONInventors: Takeo Katoh, Tomohiro Hashii, Katsuhiko Murayama, Sakae Koyata, Kazushige Takaishi
-
Publication number: 20100021688Abstract: A wafer manufacturing method includes after flattening both upper and lower surfaces of a wafer sliced from a single crystal ingot, processing the wafer having damage on both surfaces caused by the flattening, so as to obtain desired damage at least on the lower surface of the wafer, the desired damage having a damage depth ranging from 5 nm-10 ?m; forming a polysilicon layer at least on the lower surface of the wafer while the damage on the lower surface of the wafer remains; single-wafer etching the upper surface of the wafer; and final polishing the upper surface of the wafer to have a mirrored surface, after the single-wafer etching.Type: ApplicationFiled: July 21, 2009Publication date: January 28, 2010Applicant: SUMCO CORPORATIONInventors: Takeo KATOH, Tomohiro HASHII, Katsuhiko MURAYAMA, Sakae KOYATA, Kazushige TAKAISHI
-
Patent number: 7648890Abstract: A process for producing a silicon wafer comprising a single-wafer etching step of performing an etching by supplying an etching solution through a supplying-nozzle to a surface of a single and a thin-discal wafer obtained by slicing a silicon single crystal ingot and rotating the wafer to spread the etching solution over all the surface of the wafer; and a grinding step of grinding the surface of the wafer, in this order, wherein the etching solution used in the single-wafer etching step is an aqueous acid solution which contains hydrogen fluoride, nitric acid, and phosphoric acid in an amount such that the content of which by weight % at a mixing rate of fluoric acid:nitric acid:phosphoric acid is 0.5 to 40%:5 to 50%:5 to 70%, respectively.Type: GrantFiled: August 15, 2006Date of Patent: January 19, 2010Assignee: Sumco CorporationInventors: Sakae Koyata, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh
-
Publication number: 20090297867Abstract: An adhesive agent high in thixotropy is coated on the flat surface of a circular glass substrate in a uniform thickness, a silicon wafer equal in diameter is placed thereon, the adhesive agent is cured, and the silicon wafer is pasted together on the glass substrate.Type: ApplicationFiled: June 2, 2009Publication date: December 3, 2009Applicant: SUMCO CORPORATIONInventors: Takeo KATOH, Kazushige TAKAISHI
-
Publication number: 20090294918Abstract: In a state where a semiconductor wafer is not acted upon by its own weight, a shear stress on a rear surface side portion of the semiconductor wafer is higher than that on a front surface side portion of the semiconductor wafer, in a compression direction. Thereby, sag of the semiconductor wafer is reduced when the semiconductor wafer is simple-supported in a horizontal state.Type: ApplicationFiled: June 1, 2009Publication date: December 3, 2009Applicant: SUMCO CORPORATIONInventors: Takeo KATOH, Kazushige TAKAISHI
-
Publication number: 20090293919Abstract: A semiconductor wafer is cleaned by supplying a given cleaning solution to a central position of a front surface and/or a back surface of a semiconductor wafer while rotating the wafer, wherein the cleaning is conducted so as to form a water film having a thickness of 5-10 ?m on a whole surface of the wafer with the cleaning solution.Type: ApplicationFiled: May 29, 2009Publication date: December 3, 2009Applicant: SUMCO CORPORATIONInventors: Takeo Katoh, Kazushige Takaishi, Ryuichi Tanimoto
-
Publication number: 20090294910Abstract: A reinforcement member made with silicon carbide different from silicon is installed on the back face of a silicon wafer, thereby the silicon wafer is increased in Young's modulus and the wafer is less likely to deflect.Type: ApplicationFiled: June 2, 2009Publication date: December 3, 2009Applicant: SUMCO CORPORATIONInventors: Takeo KATOH, Kazushige TAKAISHI