Patents by Inventor Takeo Katoh

Takeo Katoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090297426
    Abstract: When a monocrystal is pulled up, an additive element such as boron is added to a molten silicon, and a pulling-up condition is such that a solid solution oxygen concentration is equal to or higher than 2×1018 atoms/cm3 and a chemical compound precipitation area of silicon and the additive element is formed.
    Type: Application
    Filed: June 1, 2009
    Publication date: December 3, 2009
    Applicant: SUMCO CORPORATION
    Inventors: Takeo KATOH, Kazushige TAKAISHI
  • Publication number: 20090298394
    Abstract: A silicon wafer is polished by applying a polishing solution substantially containing no abrasive grain onto a surface of a polishing pad having a given fixed grain bonded abrasive and then relatively sliding the polishing pad to a silicon wafer to polish the surface of the silicon wafer, wherein a hydroplane layer is formed by the polishing solution supplied between the surface of the silicon wafer and the surface of the polishing pad and a thickness of the hydroplane layer is controlled to change a polishing state of the surface of the silicon wafer.
    Type: Application
    Filed: May 27, 2009
    Publication date: December 3, 2009
    Applicant: SUMCO CORPORATION
    Inventors: Takeo Katoh, Ryuichi Tanimoto, Shinichi Ogata, Takeru Takushima, Kazushige Takaishi
  • Patent number: 7601644
    Abstract: This silicon wafer production process comprises in the order indicated a planarization step, in which the front surface and the rear surface of a wafer are ground or lapped, a single-wafer acid etching step, in which an acid etching liquid is supplied to the surface of the wafer while spinning and the entire wafer surface is etched to control the surface roughness Ra to 0.20 ?m or less, and a double-sided simultaneous polishing step, in which the front surface and the rear surface of the acid etched wafer are polished simultaneously. The process may comprise a single-sided polishing step, in which the top and bottom of the acid etched wafer are polished in turn, instead of the double-sided simultaneously polishing step.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: October 13, 2009
    Assignee: Sumco Corporation
    Inventors: Sakae Koyata, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh
  • Publication number: 20090181546
    Abstract: A single-wafer etching apparatus according to the present invention supplies an etchant to an upper surface of a wafer while rotating the wafer, thereby etching the upper surface of the wafer. Further, wafer elevating means moves up and down the wafer, and a lower surface blow mechanism which blows off the etchant flowing down on an edge surface of the wafer toward a radially outer side of the wafer by injection of a gas is fixed and provided without rotating together with the wafer. Furthermore, gap adjusting means controls the wafer elevating means based on detection outputs from gap detecting means for detecting a gap between the wafer and the lower surface blow mechanism, thereby adjusting the gap. The apparatus according to the present invention uniformly etches the edge portion without collapsing a chamfered shape of the edge portion of the wafer, and prevents a glitter from being produced on the edge surface of the wafer.
    Type: Application
    Filed: March 31, 2008
    Publication date: July 16, 2009
    Inventors: Takeo KATOH, Tomohiro Hashii, Katsuhiko Murayama, Sakae Koyata, Kazushige Takaishi
  • Publication number: 20090117749
    Abstract: Local shape collapse of a wafer end portion is suppressed to the minimum level, and a wafer front surface as well as a wafer end portion is uniformly etched while preventing an etchant from flowing to a wafer rear surface. There is provided an etching method of a single wafer which supplies an etchant onto a wafer front surface in a state where a single wafer having flattened front and rear surfaces is held, and etches the wafer front surface and a front surface side end portion by using a centrifugal force generated by horizontally rotating the wafer. According to this method, the etchant is intermittently supplied onto the front surface of the wafer in twice or more, supply of the etchant is stopped after the etchant for one process is supplied, and the etchant for the next process is supplied after the supplied etchant flows off from the end portion of the wafer.
    Type: Application
    Filed: October 28, 2008
    Publication date: May 7, 2009
    Inventors: Sakae KOYATA, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh
  • Publication number: 20090053894
    Abstract: A method for manufacturing an epitaxial wafer that can reduce occurrence of a surface defect or a slip formed on an epitaxial layer is provided. The manufacturing method is characterized by comprising: a smoothing step of controlling application of an etchant to a wafer surface in accordance with a surface shape of a silicon wafer to smooth the wafer surface; and an epitaxial layer forming step of forming an epitaxial layer formed of a silicon single crystal on the surface of the wafer based on epitaxial growth.
    Type: Application
    Filed: January 24, 2007
    Publication date: February 26, 2009
    Inventors: Sakae Koyata, Kazushige Takaishi, Tomohiro Hashii, Katsuhiko Murayama, Takeo Katoh
  • Patent number: 7491342
    Abstract: The present invention provides a bonded substrate fabricated to have its final active layer thickness of 200 nm or lower by performing the etching by only 1 nm to 1 ?m with a solution having an etching effect on a surface of an active layer of a bonded substrate which has been prepared by bonding two substrates after one of them having been ion-implanted and then cleaving off a portion thereof by heat treatment. SC-1 solution is used for performing the etching. A polishing, a hydrogen annealing and a sacrificial oxidation may be respectively applied to the active layer before and/or after the etching. The film thickness of this active layer can be made uniform over the entire surface area and the surface roughness of the active layer can be reduced as well.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: February 17, 2009
    Assignees: Sumco Corporation, Industry-University Cooperation Foundation, Hanyang University
    Inventors: Eiji Kamiyama, Takeo Katoh, Jea Gun Park
  • Publication number: 20090042390
    Abstract: It is possible to reduce workloads of a both-side simultaneous polishing process or a single-side polishing process, and to achieve both of the maintenance of the wafer flatness and the reduction in wafer front side roughness upon completing a flattening process. A method for manufacturing silicon wafers according to the present invention includes a flattening process 13 of grinding or lapping front and back sides of a thin disc-shaped silicon wafer obtained by slicing a silicon single crystal ingot, an etching process of immersing the silicon wafer in an etchant for controlling a silicon wafer surface shape in which a fluorochemical surfactant is uniformly mixed in an alkaline aqueous solution to etch the front and back sides of the silicon wafer, and a both-side simultaneous polishing process 16 of simultaneously polishing the front and back sides of the etched silicon wafer or a single-side polishing process of polishing the front and back sides of the etched wafer for every side, in this order.
    Type: Application
    Filed: August 9, 2007
    Publication date: February 12, 2009
    Inventors: Sakae Koyata, Takeo Katoh, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi
  • Patent number: 7488400
    Abstract: An apparatus for etching a wafer by a single-wafer process comprises a fluid supplying device which feeds an etching fluid on a wafer, and a wafer-chuck for horizontally holding the wafer. The wafer-chuck is equipped with a gas injection device for injecting a gas to the wafer, a first fluid-aspirating device, and a second fluid-aspirating device. The etching fluid supplied on the wafer is spread by a rotation of the wafer. The etching fluid is scattered by a centrifugal force, or flows down over an edge portion of the wafer and is blown-off by the gas injected from the gas injection unit, and is aspirated by the first fluid-aspirating device or the second fluid-aspirating device.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: February 10, 2009
    Assignee: Sumco Corporation
    Inventors: Sakae Koyata, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh
  • Publication number: 20090004876
    Abstract: An object of the present invention is to provide a method for etching a single wafer, which effectively realizes a high flatness of wafer and an increase in productivity thereof. In a method for etching a single wafer, a single thin disk-like wafer sliced from a silicon single crystal ingot is spun, and a front surface of the wafer is etched with an etching solution supplied thereto. In the method, a plurality of supply nozzles are disposed above and opposite to the front surface of the wafer at different portions in the radial direction of the wafer, respectively; and then one or more conditions selected from the group consisting of temperatures, kinds, and supply flow rates of etching solutions from the plurality of supply nozzles are changed.
    Type: Application
    Filed: January 24, 2007
    Publication date: January 1, 2009
    Inventors: Sakae Koyata, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh
  • Publication number: 20080214094
    Abstract: A method for manufacturing a silicon wafer comprises a slicing step of a silicon single crystal ingot to obtain sliced wafers, a single-side grinding step to grind only one side of a wafer, and a smoothing step to smooth the other side of the wafer by controlling application of etchant depending on surface profile of the other side of the wafer. According to a method of the present invention a silicon wafer that has high flatness, is removed machine working damage, and is reduced of profile change of chamfer to be minimal can be manufactured.
    Type: Application
    Filed: February 15, 2008
    Publication date: September 4, 2008
    Inventors: Takeo KATOH, Yasuyuki Hashimoto, Kazushige Takaishi, Tomohiro Hashii, Katsuhiko Murayama, Sakae Koyata
  • Publication number: 20070298614
    Abstract: An apparatus for etching a wafer by a single-wafer process comprises a fluid supplying device which feeds an etching fluid on a wafer, and a wafer-chuck for horizontally holding the wafer. The wafer-chuck is equipped with a gas injection device for injecting a gas to the wafer, a first fluid-aspirating device, and a second fluid-aspirating device. The etching fluid supplied on the wafer is spread by a rotation of the wafer. The etching fluid is scattered by a centrifugal force, or flows down over an edge portion of the wafer and is blown-off by the gas injected from the gas injection unit, and is aspirated by the first fluid-aspirating device or the second fluid-aspirating device.
    Type: Application
    Filed: August 15, 2007
    Publication date: December 27, 2007
    Inventors: Sakae Koyata, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh
  • Publication number: 20070224821
    Abstract: This silicon wafer production process comprises in the order indicated a planarization step, in which the front surface and the rear surface of a wafer are ground or lapped, a single-wafer acid etching step, in which an acid etching liquid is supplied to the surface of the wafer while spinning and the entire wafer surface is etched to control the surface roughness Ra to 0.20 ?m or less, and a double-sided simultaneous polishing step, in which the front surface and the rear surface of the acid etched wafer are polished simultaneously. The process may comprise a single-sided polishing step, in which the top and bottom of the acid etched wafer are polished in turn, instead of the double-sided simultaneously polishing step.
    Type: Application
    Filed: September 2, 2005
    Publication date: September 27, 2007
    Applicant: SUMCO CORPORATION
    Inventors: Sakae Koyata, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takatshi, Takeo Katoh
  • Publication number: 20070175863
    Abstract: An object of the present invention is to provide a single wafer etching apparatus realizing a high flatness of wafers and an increase in productivity thereof. In the single wafer etching apparatus, a single thin disk-like wafer sliced from a silicon single crystal ingot is mounted on a wafer chuck and spun thereon, and an overall front surface of the wafer is etched with an etching solution supplied thereto by centrifugal force generated by spinning the wafer 11. The singe wafer etching apparatus includes a plurality of supply nozzles 26, 27 capable of discharging the etching solution 14 from discharge openings 26a, 27a onto the front surface of the wafer 11, nozzle-moving devices each capable of independently moving the plurality of supply nozzles 28, 29, and an etching solution supplying device 30 for supplying the etching solution 14 to each of the plurality of supply nozzles and discharging the etching solution 14 from each of the discharge openings to the front surface of the wafer 11.
    Type: Application
    Filed: January 31, 2007
    Publication date: August 2, 2007
    Inventors: Sakae Koyata, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh
  • Publication number: 20070161247
    Abstract: Local shape collapse of a wafer end portion is suppressed to the minimum level, and a wafer front surface as well as a wafer end portion is uniformly etched while preventing an etchant from flowing to a wafer rear surface. There is provided an etching method of a single wafer which supplies an etchant onto a wafer front surface in a state where a single wafer having flattened front and rear surfaces is held, and etches the wafer front surface and a front surface side end portion by using a centrifugal force generated by horizontally rotating the wafer. According to this method, the etchant is intermittently supplied onto the front surface of the wafer in twice or more, supply of the etchant is stopped after the etchant for one process is supplied, and the etchant for the next process is supplied after the supplied etchant flows off from the end portion of the wafer.
    Type: Application
    Filed: July 19, 2006
    Publication date: July 12, 2007
    Inventors: Sakae KOYATA, Tomohiro HASHII, Katsuhiko MURAYAMA, Kazushige TAKAISHI, Takeo KATOH
  • Publication number: 20070087568
    Abstract: An apparatus for etching a wafer by a single-wafer process comprises a fluid supplying device which feeds an etching fluid on a wafer, and a wafer-chuck for horizontally holding the wafer. The wafer-chuck is equipped with a gas injection device for injecting a gas to the wafer, a first fluid-aspirating device, and a second fluid-aspirating device. The etching fluid supplied on the wafer is spread by a rotation of the wafer. The etching fluid is scattered by a centrifugal force, or flows down over an edge portion of the wafer and is blown-off by the gas injected from the gas injection unit, and is aspirated by the first fluid-aspirating device or the second fluid-aspirating device.
    Type: Application
    Filed: October 17, 2006
    Publication date: April 19, 2007
    Inventors: Sakae Koyata, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh
  • Publication number: 20070042567
    Abstract: A process for producing a silicon wafer comprising a single-wafer etching step of performing an etching by supplying an etching solution through a supplying-nozzle to a surface of a single and a thin-discal wafer obtained by slicing a silicon single crystal ingot and rotating the wafer to spread the etching solution over all the surface of the wafer; and a grinding step of grinding the surface of the wafer, in this order, wherein the etching solution used in the single-wafer etching step is an aqueous acid solution which contains hydrogen fluoride, nitric acid, and phosphoric acid in an amount such that the content of which by weight % at a mixing rate of fluoric acid: nitric acid: phosphoric acid is 0.5 to 40%: 5 to 50%: 5 to 70%, respectively.
    Type: Application
    Filed: August 15, 2006
    Publication date: February 22, 2007
    Inventors: Sakae Koyata, Tomohiro Hashii, Katsuhiko Murayama, Kazushige Takaishi, Takeo Katoh
  • Publication number: 20060246723
    Abstract: A method for controlling a selection ratio of a chemical-mechanical-polishing slurry composition for polishing and ablating an oxide layer selectively in relation to a nitride layer, the method includes: a step of confirming a polishing-rate selection ratio of an oxide layer to a nitride layer of a chemical-mechanical-polishing slurry composition which includes ceria polishing particles, a dispersing agent, and an anionic additive, while a concentration of the anionic additive is changed; and a step of adjusting the concentration of the anionic additive to attain a desired selection ratio of the slurry composition, on the basis of the confirmed polishing-rate selection ratio, thereby controlling the selection ratio of the slurry composition.
    Type: Application
    Filed: December 25, 2003
    Publication date: November 2, 2006
    Applicant: SUMITOMO MITSUBISHI SILICON CORPORATION
    Inventors: Jea Park, Un Paik, Jin Park, Takeo Katoh
  • Publication number: 20060207188
    Abstract: The present invention relates to a CMP abrasive comprising a ceria slurry and a chemical additive having two or more functional groups by mixing and synthesizing a polymeric molecule and a monomer. Also, the present invention relates to a method for a manufacturing CMP abrasive by providing a ceria slurry, manufacturing a chemical additive having two or more functional groups by mixing and synthesizing of the polymeric molecule and the monomer in a reactor, and mixing said slurry and said chemical additive. Therefore, when the abrasive according to the present invention is used as an STI CMP abrasive, it is possible to apply the abrasive to the patterning process required in the very large scale integration semiconductor process. Furthermore, the CMP abrasive of the present invention has a superior removal rate, superior polishing selectivity, superior within wafer non-uniformity (WIWNU), and minimized occurrence of micro scratches.
    Type: Application
    Filed: May 14, 2004
    Publication date: September 21, 2006
    Inventors: Un-Gyu Paik, Jea-Gun Park, Sang-Kyun Kim, Takeo Katoh, Yong-Kook Park
  • Publication number: 20060118935
    Abstract: The present invention provides a bonded substrate fabricated to have its final active layer thickness of 200 nm or lower by performing the etching by only 1 nm to 1 ?m with a solution having an etching effect on a surface of an active layer of a bonded substrate which has been prepared by bonding two substrates after one of them having been ion-implanted and then cleaving off a portion thereof by heat treatment. SC-1 solution is used for performing the etching. A polishing, a hydrogen annealing and a sacrificial oxidation may be respectively applied to the active layer before and/or after the etching. The film thickness of this active layer can be made uniform over the entire surface area and the surface roughness of the active layer can be reduced as well.
    Type: Application
    Filed: April 2, 2004
    Publication date: June 8, 2006
    Inventors: Eiji Kamiyama, Takeo Katoh, Jea Park