Abstract: An immunosuppressive agent containing a substance that is selected from anti-CD80 antibodies and anti-PD-L1 antibodies and that promotes binding between PD-L1 and PD-1.

Abstract: A document processing system includes a character code changing means for recording font data of characters in a sentence in an order of appearance of the characters and changes character codes of the recorded font data into converted character codes consisting of an order number of the font data; a conversion table creating means for creating a conversion table showing correspondences between the character codes and converted character codes; and an output means for outputting characters in fonts according to the font data.

Abstract: A method for manufacturing a semiconductor device of the present invention has the step of forming an insulation material on a main surface of a semiconductor substrate. A groove is formed to extend from the surface of the material film to the substrate. The groove is buried with a first insulation film. By use of the first insulation film as an etching mask, the material film is removed, so that a projecting portion projecting to the first insulation film from the main surface can be obtained. A second insulation film is formed on a side surface of the projecting portion in a sloped shape, which is from the top portion of the projecting portion to the main surface.

Abstract: An npn bipolar transistor and a p-channel MOS transistor are formed on a p-type silicon substrate. The outer base electrode of the npn bipolar transistor and the gate electrode of the p-channel MOS transistor contain a p-type impurity and are composed of films consisting of the same material. The inner and outer bases are formed in a surface region of the p-type silicon substrate. The outer base is connected to the outer base electrode. The emitter electrode of the npn bipolar transistor is formed on the inner base. A laminated film constituted by a silicon oxide film and a silicon nitride film is formed on a p-type silicon substrate at a position between the outer base electrode and the emitter electrode.

Abstract: A semiconductor device comprises a p-type semiconductor substrate, an n-type semiconductor well formed on the substrate and connected to a positive power supply, a p-type semiconductor source formed within the n-type semiconductor well, a p-type semiconductor layer formed within the n-type semiconductor well and having a lower impurity concentration than the p-type semiconductor source, a first gate electrode formed over a region between the p-type semiconductor source and the p-type semiconductor layer through an insulating film, an n-type semiconductor emitter formed over the p-type semiconductor layer within the n-type semiconductor well, a first conductive layer formed over the n-type semiconductor well to connect with said p-type semiconductor source.

Abstract: A semiconductor integrated circuit device having a bipolar transistor and contact in the form of a wired layer by using different impurities for doping the emitter electrode and the wired layer of the device, both of which are made of polysilicon. The emitter electrode, formed on an emitter region of a p-type silicon semiconductor substrate, is doped with an n-type impurity having a low diffusion coefficient. A polysilicon wired layer, formed on an impurity diffusion region in an active region of the semiconductor substrate, is doped with another impurity that can effectively destroy native oxide films. With such an arrangement of selectively using impurities, the temperature of thermally treating the emitter region can be less than 850.degree. C.

Abstract: A method of manufacturing a semiconductor device. A semiconductor substrate is prepared and a gate oxide film is formed on a surface of the semiconductor substrate. The gate oxide film is selectively removed to expose portions of the semiconductor substrate and a first polysilicon layer is formed on a resultant semiconductor structure. Impurities are implanted in the polysilicon layer and a resultant semiconductor structure is annealed to activate the impurities. The first polysilicon layer is patterned to form a base electrode of the bipolar transistor and a source drain electrode of the MOS transistor. An insulating layer is then formed on a resultant semiconductor structure. Portions of the semiconductor substrate are then selectively exposed and a second polysilicon layer is formed on a resultant semiconductor structure. The second polysilicon layer is then patterned to form an emitter electrode of the bipolar transistor.

Abstract: A semiconductor device of this invention includes a bipolar transistor and MOS transistors which are formed on the same semiconductor substrate. The bipolar transistor is hetero-bipolar transistor having a hetero junction. The hetero-bipolar transistor is a bipolar transistor of double-hetero structure in which a material used for forming the base region thereof has a band gap narrower than a material used for forming the emitter and collector regions thereof.

Abstract: A method for manufacturing a semiconductor device of the present invention has the step of forming an insulation material on a main surface of a semiconductor substrate. A groove is formed to extend from the surface of the material film to the substrate. The groove is buried with a first insulation film. By use of the first insulation film as an etching mask, the material film is removed, so that a projecting portion projecting to the first insulation film from the main surface can be obtained. A second insulation film is formed on a side surface or the projecting portion in a slope shape, which is from the top portion of the projecting portion to the main surface.

Abstract: A semiconductor device has a first P type well region (11) formed on an N type semiconductor substrate (10) and a second N type well region (12) formed so as to enclose the first well region. A third N type well region (13) formed on the semiconductor substrate is enclosed by a fourth P type well region (14). The first well region adjoins and is electrically connected to the fourth well region. Contact regions (15, 16) are formed on the first and third well regions to apply a bias voltage to the PN junction between the first and third well regions. An NMOS FET is formed in the first well region and a PMOS FET is formed in the third well region. The drain currents of the NMOS FET and PMOS FET are controlled by changing the reverse bias voltage applied to the two contact regions (15, 16). The depth of the first well region (11) is such that a depletion layer extending below the NMOS FET gate electrode (50) can be connected to a depletion layer formed at an interface between the first and second well regions.

Abstract: A semiconductor device of this invention includes an N-type semiconductor region functioning as a collector of a bipolar transistor, a silicon dioxide film doped with boron and formed in contact with the surface of the N-type semiconductor region, a P-type semiconductor region formed in contact with the silicon dioxide film doped with boron in the N-type semiconductor region and functioning as a base of the bipolar transistor, and an N-type semiconductor region formed in the P-type semiconductor region and functioning as an emitter of the bipolar transistor.

Abstract: In a semiconductor device, an emitter electrode has a polysilicon layer provided in a first contact hole and on a first insulating film. The polysilicon layer is in contact with an emitter region and is covered with a metal layer. A second contact hole is provided on a part of a second insulating film located on a substantially flat portion of the metal layer. A third contact hole is provided in those portions of the first insulating film and a second insulating layer which are located on a base region.

Abstract: A semiconductor device of this invention includes an N-type semiconductor region functioning as a collector of a bipolar transistor, a silicon dioxide film doped with boron and formed in contact with the surface of the N-type semiconductor region, a P-type semiconductor region formed in contact with the silicon dioxide film doped with boron in the N-type semiconductor region and functioning as a base of the bipolar transistor, and an N-type semiconductor region formed in the P-type semiconductor region and functioning as an emitter of the bipolar transistor.

Abstract: A semiconductor device of the present invention includes a bipolar transistor and MOS transistors which are formed on the same semiconductor substrate. The bipolar transistor is heterojunction transistor having a hetero junction. The hetero-bipolar transistor is a bipolar transistor of double-hetero structure in which a material used for forming the base region thereof has a band gap narrower than a material used for forming the emitter and collector regions thereof.

Abstract: A method of manufacturing a semiconductor device. A semiconductor substrate is prepared and a gate oxide film is formed on a surface of the semiconductor substrate. The gate oxide film is selectively removed to expose portions of the semiconductor substrate and a first polysilicon layer is formed on a resultant semiconductor structure. Impurities are implanted in the polysilicon layer and a resultant semiconductor structure is annealed to activate the impurities. The first polysilicon layer is patterned to form a base electrode of the bipolar transistor and a gate and/or drain electrode of the MOS transistor. An insulating layer is then formed on a resultant semiconductor structure. Portions of the semiconductor substrate are then selectively exposed and a second polysilicon layer is formed on a resultant semiconductor structure. The second polysilicon layer is then patterned to form an emitter electrode of the bipolar transistor.

Abstract: A contact hole for guiding an emitter electrode of bipolar transistors continuously arrayed and a contact hole for guiding a base electrode are positioned not to be arranged in the continuous array direction of the bipolar transistors. Also, the emitter electrode and the base electrode are respectively drawn from these contact holes in two directions different from the continuous array direction of the bipolar transistors. At least one of the base electrode and the emitter electrode is formed on a conductive layer of a polycide structure contacting an active region in a substrate to be connected.

Abstract: A semiconductor device of the invention has a p.sup.+ -type silicon source region, an insulating film formed on the source region and having a contact hole, and a wiring electrode connected to the source region through the contact hole. The wiring electrode has a Ti layer formed on the insulating film and an exposed surface of the source region, a TiN layer formed on the Ti layer, and an Al layer formed on the TiN layer.

Abstract: Disclosed here in is a semiconductor integrated circuit comprising a substrate, a memory cell array having a plurality of memory cells arranged in rows and columns, a plurality of word lines, and a plurality of bit lines, and a plurality of word-line drive circuits located near the memory cell array. Each of the word-line drive circuits is a Bi-NMOS circuit which comprises a bipolar transistor for pulling up the potential of the word line and an N-channel MOS transistor for pulling down the potential of the word line. The collector layers of the bipolar transistors are formed of one and the same layer.

Abstract: A semiconductor device having CMOS transistors and bipolar transistors is disclosed. A P-type high concentration buried region is formed in the surface region of the semiconductor substrate. An N-type epitaxial layer is formed on the buried region. The semiconductor device includes a second well region of a PMOS transistor that is formed by introducing an N-type impurity into a part of the epitaxial layer, and a first well region of a bipolar transistor that is formed without introducing the N-impurity, after the formation of the epitaxial layer.

Abstract: A method of manufacturing a semiconductor device. A semiconductor substrate is prepared and a gate oxide film is formed on a surface of the semiconductor substrate. The gate oxide film is selectively removed to expose portions of the semiconductor substrate and a first polysilicon layer is formed on a resultant semiconductor structure. Impurities are implanted in the polysilicon layer and a resultant semiconductor structure is annealed to activate the impurities. The first polysilicon layer is patterned to form a base electrode of the bipolar transistor and a gate and/or drain electrode of the MOS transistor. An insulating layer is then formed on a resultant semiconductor structure. Portions of the semiconductor substrate are then selectively exposed and a second polysilicon layer is formed on a resultant semiconductor structure. The second polysilicon layer is then patterned to form an emitter electrode of the bipolar transistor.