Patents by Inventor Takeo Maeda

Takeo Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5091760
    Abstract: A semiconductor device includes a semiconductor substrate, a bipolar transistor and a MOS transistor. The bipolar transistor is formed on the semiconductor substrate and has electrodes. A base electrode of the bipolar transistor and the electrodes of the MOS transistor contain the same kind of impurity so as to form a single layer.
    Type: Grant
    Filed: April 10, 1990
    Date of Patent: February 25, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeo Maeda, Hiroshi Momose
  • Patent number: 5075752
    Abstract: A Bi-CMOS semiconductor device includes a P-type semiconductor substrate, an N-type buried layer formed in the semiconductor substrate, a P-type well region formed on the buried layer, and an N-channel MOS transistor formed in a first predetermined area of the well region. The Bi-CMOS semiconductor device further includes an N-type surrounding layer formed to surround the well region in cooperation with the buried layer. The surrounding layer electrically isolates the well region from the substrate and the other P-type well region.
    Type: Grant
    Filed: February 16, 1990
    Date of Patent: December 24, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeo Maeda, Syuso Fujii
  • Patent number: 5014106
    Abstract: A semiconductor device for use in a hybrid LSI circuit is disclosed which comprises MOSFETs and at least two bipolar transistor--all formed on the same semiconductor substrate. More specifically, p.sup.+ -type buried diffusion layers and p.sup.+ -type buried diffusion layers are formed on a P-type semiconductor substrate. An N-type epitaxial layer is formed on these buried layers. N-type well-regions and a P-type well-region are formed in the selected portions of the N-type epitaxial layer. A P-channel MOSFET and an N-channel MOSFET are formed in the N-type well-region and the P-type well-region, respectively. A first bipolar transistor is formed on the N-type epitaxial layer. A second bipolar transistor is formed on the N-type well-region which has an impurity concentration higher than that of the N-type epitaxial layer.
    Type: Grant
    Filed: March 7, 1990
    Date of Patent: May 7, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeo Maeda, Masayoshi Higashizono
  • Patent number: 4931407
    Abstract: A method for manufacturing MOS and bipolar transistors is proposed which includes MOS and bipolar transistors. The method comprises implanting impurity ions in a channel formation region with a dummy gate insulating film interposed and, subsequent to forming a gate oxide film on the surface of the resultant structure, impurity ions are implanted into an internal base region of the bipolar transistor.
    Type: Grant
    Filed: June 24, 1988
    Date of Patent: June 5, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeo Maeda, Koji Makita
  • Patent number: 4900257
    Abstract: A semiconductor device has a multilayer comprising a refractory metal silicide and a metal nitride on a silicon layer. The metal nitride prevents the silicon layer from being oxidized so that a good ohmic contact is obtained. A method of manufacturing the semniconductor device comprises steps of forming a polysilicon layer, implanting impurity ions into the polysilicon, removing a self oxidation film from the polysilicon layer, sequentially forming refractory metal and its nitride, patterning, and silicifying the metal. The method provides a semiconductor device having a good ohmic contact, a reduced resistivity of interconnections and high reliability.
    Type: Grant
    Filed: April 14, 1988
    Date of Patent: February 13, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeo Maeda
  • Patent number: 4769337
    Abstract: A method of manufacturing a semiconductor device, comprises the process of forming first and second well regions, which are of N-type and P-type, respectively, in a silicon body, forming a base layer of P-type in the first well region, forming an emitter layer of N-type in the base layer, forming source and drain layers of N-type in the second well region, forming a polysilicon emitter electrode on the emitter layer, and ion-implanting impurities of N-type into an interface between the emitter layer and the emitter electrode, so as to break down an insulative layer at the interface.
    Type: Grant
    Filed: May 8, 1987
    Date of Patent: September 6, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeo Maeda
  • Patent number: 4663825
    Abstract: A method of manufacturing a semiconductor device comprises the steps of forming a gate electrode on a silicon substrate of a p-conductivity type and source and in the drain regions of an n-conductivity type substrate so as to interpose the gate electrode therebetween; depositing silicon on the source and drain regions to form a polysilicon wiring layer; and ion-implanting an impurity to an interface between the source and drain regions and the polysilicon wiring layer at acceleration voltage of 40 keV and a dose of 5.times.10.sup.15 cm.sup.-2 to mechanically break down an oxide film formed at said interface.
    Type: Grant
    Filed: September 25, 1985
    Date of Patent: May 12, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeo Maeda
  • Patent number: 4643777
    Abstract: There is disclosed a method of manufacturing a semiconductor device comprising the steps of forming a polysilicon film on a semiconductor substrate through an oxidation film, forming a mask of a predetermined pattern on the polysilicon film, forming a molybdenum film on the polysilicon film, and silicifying those regions of said molybdenum film not covered by the mask so that a structure of the uncovered molybdenum film regions and those regions of the polysilicon film located under the uncovered molybdenum regions have low resistance, while a region of the molybdenum film covered by the mask has high resistance.
    Type: Grant
    Filed: December 19, 1984
    Date of Patent: February 17, 1987
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takeo Maeda
  • Patent number: 4540500
    Abstract: A low temperature sinterable oxide magnetic material prepared by adding 0.1 to 5% by weight of glass containing 3 to 50 mol % of Li.sub.2 O, 10 to 97 mol % of B.sub.2 O.sub.3 and 0 to 70 mol % of SiO.sub.2 to ferrite containing at least 0.5 mol % of Li.sub.2 O. Especially, when a glass containing 10-28 mol % of Li.sub.2 O, 34 to 66 mol % of B.sub.2 O.sub.3, and 15 to 45 mol % of SiO.sub.2 is used, the sintering temperature can be reduced to about 1,000.degree. C. or less.
    Type: Grant
    Filed: October 20, 1983
    Date of Patent: September 10, 1985
    Assignee: Fuji Electrochemical Co., Ltd.
    Inventors: Michihiro Torii, Tomoyoshi Kosaka, Takeo Maeda, Hiroshi Rikukawa
  • Patent number: 4384248
    Abstract: Shortcircuit in an arm including a series connection of GTO's and reactors of an inverter is detected by sensing a voltage across the reactor. In one method, the shortcircuit in the arm is detected when voltages are coincidently applied to a P-line arm reactor and an N-line arm reactor for a predetermined time period. In another method, it is detected when an integrated value of a voltage across at least one of the reactors exceeds a predetermined level.
    Type: Grant
    Filed: June 17, 1980
    Date of Patent: May 17, 1983
    Assignee: Hitachi, Ltd.
    Inventors: Yasuo Matsuda, Kazuo Honda, Takeo Maeda
  • Patent number: 4336475
    Abstract: The present invention relates to a slotless, brushless motor comprising a permanent magnet rotor rotationary together with a shaft and a stationary armature coil disposed in opposition to the rotor.The armature coil comprises a coil portion concentrically wound, an adjacent coil portion formed in sequence from the coil portion and concentrically wound, a coil performed on a plane by a plurality of the coil portions, N coils (N is integer) laid on each other and different in a phase respectively, sheets disposed between said N coils and a supporting member supporting the coils and the sheets made integral.
    Type: Grant
    Filed: August 14, 1979
    Date of Patent: June 22, 1982
    Assignee: Hitachi, Ltd.
    Inventors: Shigeki Morinaga, Kunio Miyashita, Tadashi Takahashi, Takeo Maeda, Seizi Yamashita
  • Patent number: 4194919
    Abstract: The flexural strength of hydraulic cement compositions is increased by incorporating water-soluble epoxy resins, aliphatic amines and cement dispersants into cement compositions and hardening the compositions.
    Type: Grant
    Filed: March 29, 1978
    Date of Patent: March 25, 1980
    Assignee: Kao Soap Co., Ltd.
    Inventors: Kenichi Hattori, Shinji Iwai, Toshio Okuyama, Yuji Nakagawa, Takeo Maeda, Yasuyuki Kawakatsu
  • Patent number: 4173193
    Abstract: An apparatus for controlling an electric sewing machine has a mechanism for transmitting the driving torque of a motor to the sewing machine to drive the same, a mechanism for imparting braking power to the sewing machine to stop the same, a mechanism for stopping the needle of said sewing machine at desired positions in its stroke and controlling means adapted to control these mechanisms. At least a part of the controlling means is constituted by a microcomputer. The signal input to the microcomputer is provided in synchronization with a synchronizing clock signal, and only such input signals as required in respective periods of operation are checked in each of the periods, so that the checking of the input signals is facilitated and accidents due to erroneous operation are avoided.
    Type: Grant
    Filed: January 4, 1978
    Date of Patent: November 6, 1979
    Assignee: Hitachi, Ltd.
    Inventors: Shigeki Morinaga, Takeo Maeda, Tadashi Takahashi, Kosho Ishizaki
  • Patent number: 4156899
    Abstract: A current source inverter circuit having a plurality of branches, each branch consisting of a pair of thyristors adapted to be switched on alternatingly for power supply from a D. C. power source and diodes connected in series to the thyristors. To each connection point between a thyristor and a diode, there is connected one end of one of a plurality of commutating capacitors, while the other ends of the capacitors are connected in common. An auxiliary charging source is provided between the common connection of the commutating capacitors and one of the terminals of the D. C. source for performing an auxiliary charging for each commutating capacitor through a respective thyristor. Between one of the terminals of the D. C. power source and the common connection of the commutating capacitors, a series circuit consisting of a diode and an auxiliary D. C. source is provided constituting a by-pass for the charging voltage of the commutating capacitor when the associated thyristor is in the ON state.
    Type: Grant
    Filed: May 25, 1977
    Date of Patent: May 29, 1979
    Assignee: Hitachi, Ltd.
    Inventors: Yasuo Matsuda, Takeo Maeda, Takuji Matsumura
  • Patent number: 4099108
    Abstract: An induction motor is operated by a power supply of variable voltage and variable frequency. The voltage and frequency of the variable-voltage variable-frequency power supply is changed by a control circuit to accelerate or decelerate the induction motor. For slowly controlling the speed of the induction motor, the ratio of the output voltage to the output frequency of the variable-voltage variable-frequency power supply is maintained substantially constant. The control circuit includes a voltage correcting means which, in response to a command for sudden acceleration or deceleration of the speed of the motor, corrects the output voltage of the power supply in accordance with the acceleration or deceleration rate and the prevailing magnitude of the output frequency of the variable-voltage variable-frequency power supply.
    Type: Grant
    Filed: August 20, 1976
    Date of Patent: July 4, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Tadashi Okawa, Yasuo Matsuda, Hiroshi Hayashida, Takeo Maeda
  • Patent number: 4012679
    Abstract: A method and an apparatus for controlling the operation of the synchronous motor are disclosed in which the synchronous motor is started with a starting power supply and operated with a steadying power supply. The starting power supply is adapted to alternately repeat acceleration and deceleration of the synchronous motor in the neighborhood of the frequency thereby to bring the synchronous motor into the point where the synchronous motor is in synchronism with the steadying power supply. The starting power supply comprises a current control circuit and a phase angle control circuit, which circuits control the motor current in such a manner as to prevent the voltage drop due to the synchronous reactance of the motor from exceeding the induced voltage of the motor, while at the same time controlling the power factor angle to be in the range from a lead 90.degree. to the angle corresponding to a maximum output point produced by said motor current.
    Type: Grant
    Filed: January 23, 1975
    Date of Patent: March 15, 1977
    Assignee: Hitachi, Ltd.
    Inventors: Yasuo Matsuda, Takeo Maeda, Kouzou Watanabe, Kazuo Honda, Hironori Okuda, Kunio Miyashita, Yasuyuki Sugiura
  • Patent number: 3997825
    Abstract: In the control of a synchronous motor driven by a power converter of voltage source type, the phase of the current flowing into the motor is detected and gate signals are produced on the basis of the phase of the current, so that the output frequency of the power converter is controlled by the gate signals so as to control the motor.
    Type: Grant
    Filed: October 7, 1974
    Date of Patent: December 14, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Kunio Miyasita, Hironori Okuda, Yasuyuki Sugiura, Takeo Maeda, Yasuo Matsuda, Kazuo Honda
  • Patent number: 3939387
    Abstract: In a variable frequency power converter of a current type for driving an AC motor including a rectifier, an inverter, and a smoothing reactor disposed on a DC transmission line between the rectifier and the inverter, there are provided a series circuit having a switching circuit and a smoothing capacitor on the DC input side of the inverter and a feedback circuit having controlled rectifier elements and commutation reactors for feeding back the reactive power of the AC motor. The power converter operates as a current type converter until the output frequency of the converter reaches a predetermined value under the condition that the switching circuit and the controlled rectifier elements are non-conductive, and operates as a voltage type converter when the output frequency has reached the predetermined value under the condition that the switching circuit and the controlled rectifier elements are conductive.
    Type: Grant
    Filed: April 19, 1974
    Date of Patent: February 17, 1976
    Assignee: Hitachi, Ltd.
    Inventor: Takeo Maeda