Abstract: Current drive efficiency is deteriorated in the conventional FET. The FET 20 includes an electrode film 24a provided over the semiconductor substrate 10 and a stressor film 24b that is provided on the electrode film 24a and constitutes a gate electrode 24 together with the electrode film 24a. Each of the electrode film 24a and the stressor film 24b is composed of a metal, a metallic nitride or a metallic silicide. The stressor film 24b is capable of exhibiting a compressive stress over the semiconductor substrate 10.

Abstract: A gate insulating film is formed on a substrate. Next, a gate electrode film is formed on the gate insulating film. A mask film is formed on a portion of the gate electrode film. The gate electrode film is selectively removed by etching using the mask film as a mask. A gate sidewall film is formed so as to be in contact with the lateral surfaces of the mask film and the gate electrode film. The mask film is formed of a laminated film in which at least a first film, a second film and a third film are laminated in this order. The second film has a higher etching selectivity ratio than that of the third film with respect to the gate sidewall film. The third film has a higher etching selectivity ratio than that of the second film with respect to the gate electrode film.

Abstract: A semiconductor device includes a substrate, a first gate insulation film formed over a first device forming region disposed in the substrate, a second gate insulation film formed over a second device forming region disposed in the substrate, a lower gate electrode film formed over the first gate insulation film and over the second gate insulation film and comprising a metal nitride film; a mask film formed over the lower gate electrode film situated over the second gate insulation film, and an upper gate electrode film formed over the lower gate electrode film and over the mask film.

Abstract: Device isolation regions for isolating a device forming region are formed over a substrate. Subsequently, a gate insulation film is formed over the device forming region. Then, a lower gate electrode film comprised of a metal nitride film is formed over the gate insulation film. Further, a heat treatment is performed to the lower gate electrode film and then an upper gate electrode film is formed over the lower gate electrode film.

Abstract: A semiconductor device with integrated MIS field-effect transistors includes a first transistor including a first gate electrode having a composition represented by MAx, and a second transistor including a second gate electrode having a composition represented by MAy, in which M includes at least one metal element selected from the group consisting of W, Mo, Ni, Pt, Ta, Pd, Co, and Ti, A includes at least one of silicon and germanium, and 0<x?3, and 0<y?3, and x and y are different from each other.

Abstract: Current drive efficiency is deteriorated in the conventional FET. The FET 20 includes an electrode film 24a provided over the semiconductor substrate 10 and a stressor film 24b that is provided on the electrode film 24a and constitutes a gate electrode 24 together with the electrode film 24a. Each of the electrode film 24a and the stressor film 24b is composed of a metal, a metallic nitride or a metallic silicide. The stressor film 24b is capable of exhibiting a compressive stress over the semiconductor substrate 10.

Abstract: A semiconductor device includes a semiconductor substrate, a first gate insulating film, a silicon-containing second gate insulating film, and a first gate electrode. The first gate insulating film is formed on the semiconductor substrate and made of a material having a dielectric constant higher than a dielectric constant of silicon oxide or silicon oxynitride. The silicon-containing second gate insulating film is formed on the first gate insulating film. The first gate electrode is formed on the silicon-containing second gate insulating film and includes a metal nitride layer. The first gate insulating film, the silicon-containing second gate insulating film and the metal nitride layer form part of the pMOSFET.

Abstract: A gate insulating film is formed on a substrate. Next, a gate electrode film is formed on the gate insulating film. A mask film is formed on a portion of the gate electrode film. The gate electrode film is selectively removed by etching using the mask film as a mask. A gate sidewall film is formed so as to be in contact with the lateral surfaces of the mask film and the gate electrode film. The mask film is formed of a laminated film in which at least a first film, a second film and a third film are laminated in this order. The second film has a higher etching selectivity ratio than that of the third film with respect to the gate sidewall film. The third film has a higher etching selectivity ratio than that of the second film with respect to the gate electrode film.

Abstract: Device isolation regions for isolating a device forming region are formed over a substrate. Subsequently, a gate insulation film is formed over the device forming region. Then, a lower gate electrode film comprised of a metal nitride film is formed over the gate insulation film. Further, a heat treatment is performed to the lower gate electrode film and then an upper gate electrode film is formed over the lower gate electrode film.

Abstract: There is provided a semiconductor device including: a semiconductor substrate; a gate insulating film formed on the semiconductor substrate; a work function control layer formed on the gate insulating film; a first silicide layer formed on the work function control layer; a polysilicon gate electrode formed on the first silicide layer; and a source region and a drain region formed on opposite sides of a region under the polysilicon gate electrode in the semiconductor substrate.

Abstract: It is intended to provide a substrate structure ensuring a shielding property and a heat discharge property of a resin part that collectively covers a plurality of electronic components and capable of downsizing, thinning, and a reduction in number of components. The substrate structure 20 of the first embodiment is provided with a substrate 21, a plurality of electronic components 22 mounted along the substrate 21, and a resin part 25 that covers the electronic components 22 and is in close contact with the substrate 21. In the substrate structure 20, the resin part 25 is provided with a reinforcing heat discharge layer 26 covering the electronic components 22 and having a heat conductivity and a reinforcing property and a shield layer 27 covering the reinforcing heat discharge layer 26, and a surface o28 of the shield layer 27 is formed into a predetermined shape corresponding to a surface structure of the display device 30 adjacent to the resin part 25.

Abstract: A semiconductor device with integrated MIS field-effect transistors includes a first transistor including a first gate electrode having a composition represented by MAx, and a second transistor including a second gate electrode having a composition represented by MAy, in which M includes at least one metal element selected from the group consisting of W, Mo, Ni, Pt, Ta, Pd, Co, and Ti, A includes at least one of silicon and germanium, and 0<x?3, and 0<y?3, and x and y are different from each other.

Abstract: A semiconductor device with integrated MIS field-effect transistors includes a first transistor containing a first gate electrode having a composition represented by MAx and a second transistor containing a second gate electrode having a composition represented by MAy, wherein M is at least one metal element selected from the group consisting of W, Mo, Ni, Pt, Ta, Pd, Co and Ti; A is silicon and/or germanium; 0<x?3 and 0<y?3, and x and y are different from each other.

Abstract: A portable terminal in which, even when an impact caused by dropping or the like acts on an engaging portion of a second rotating member, it is possible to prevent a lock pin for fixing the second rotating member, and an engaging portion from being broken is provided. A second housing portion 56 in which a magnet 63 of a second engaging portion 46 is disposed attracts an engaging pin 45 formed by a magnetic material, by a magnetic force to project the engaging pin 45 from the surface 11A of a first case 11, and a second case 12 is caused to rotate about a second rotating axis 32, whereby a second projecting portion 52 is housed in the second housing portion 56 and the engaging pin 45 is locked. The second projecting portion 52 is rotatable about the axis of a first projecting portion 51.

Abstract: It is intended to provide a substrate structure ensuring a shielding property and a heat discharge property of a resin part that collectively covers a plurality of electronic components and capable of downsizing, thinning, and a reduction in number of components. The substrate structure 20 of the first embodiment is provided with a substrate 21, a plurality of electronic components 22 mounted along the substrate 21, and a resin part 25 that covers the electronic components 22 and is in close contact with the substrate 21. In the substrate structure 20, the resin part 25 is provided with a reinforcing heat discharge layer 26 covering the electronic components 22 and having a heat conductivity and a reinforcing property and a shield layer 27 covering the reinforcing heat discharge layer 26, and a surface o28 of the shield layer 27 is formed into a predetermined shape corresponding to a surface structure of the display device 30 adjacent to the resin part 25.

Abstract: There is provided a semiconductor device which can control a reaction caused between a gate electrode and a high-k gate dielectric film, and which has an element structure suitable for higher integration and speed-up. The semiconductor device has an insulated-gate field-effect transistor, wherein the insulated-gate field-effect transistor has: a gate insulating film including a high-k dielectric film; and a gate electrode with a laminated structure including a first conductive layer, and a second conductive layer which has a resistivity lower than that of the first conductive layer, and the first conductive layer is provided on and in contact with the high-k dielectric film, and includes titanium nitride with a density of 5 g/cm3 or more.

Abstract: A semiconductor device with integrated MIS field-effect transistors includes a first transistor containing a first gate electrode having a composition represented by MAx and a second transistor containing a second gate electrode having a composition represented by MAy, wherein M is at least one metal element selected from the group consisting of W, Mo, Ni, Pt, Ta, Pd, Co and Ti; A is silicon and/or germanium; 0<x?3 and 0<y?3, and x and y are different from each other.

Abstract: Current drive efficiency is deteriorated in the conventional FET. The FET 20 includes an electrode film 24a provided over the semiconductor substrate 10 and a stressor film 24b that is provided on the electrode film 24a and constitutes a gate electrode 24 together with the electrode film 24a. Each of the electrode film 24a and the stressor film 24b is composed of a metal, a metallic nitride or a metallic silicide. The stressor film 24b is capable of exhibiting a compressive stress over the semiconductor substrate 10.

Abstract: An object of this invention is to prevent the NBTI degradation which may occur following the recent progress in miniaturization of the semiconductor device. By using a silicon nitride film, in which a concentration of Si—H bonds is not greater than 1×1021 cm?3, at least for a liner film or a second sidewall insulating film, the NBTI lifetime of the p-type MOS FET can be improved to be 1×109 seconds, which secures sufficient lifetime for the semiconductor integrated circuit device.

Abstract: The present invention provides a structure for a semiconductor device, capable of eliminating the generation of defective products due to poor connection. In the present semiconductor device, an n-type high concentration diffusion layer 2 is selectively formed on the P-type silicon substrate 1, and on the diffusion layer 2, a silicon oxide film 3 is formed as a first interlayer insulating film 3. A silicon plug 4 is disposed on the n-type high concentration diffusion layer 2. On the top end surface of the polysilicon plug 4, a silicide pad 5 is formed in a self-aligning manner such that the width of the silicide pad 5 is larger than that of the polysilicon plug 4. A second interlayer insulating film is formed so as to cover the first interlayer insulating film 3 and the silicide pad 5, and a tungsten plug 7 is disposed on the silicide pad 5. On the second interlayer insulating film, wiring 8, made of an aluminum-copper alloy and connected to the tungsten plug, is formed.