Abstract: A field effect transistor includes a lower gate electrode, upper gate electrode, first, second, and third barrier films, and source and drain. The lower gate electrode is formed from silicon on a silicon substrate via a gate insulating film. The upper gate electrode is formed from copper above the lower gate electrode. The first barrier film has a conductivity capable of supplying to the lower gate electrode a current enough to drive a channel portion, covers the lower surface of the upper gate electrode, and impedes diffusion of copper. The second barrier film has a lower end in contact with the first barrier film, covers the side surfaces of the upper gate electrode, and impedes diffusion of copper. The third barrier film has an end portion in contact with the second barrier film, covers the upper surface of the upper gate electrode, and impedes diffusion of copper. The source and drain are formed in the silicon substrate to sandwich a region under the lower gate electrode.

Abstract: The interval between gate electrodes in a memory cell portion and the interval between gate electrodes in a peripheral circuit portion are set so as to have a relation with the widths of sidewall insulating films of the gate electrodes. Using an etching stopper film, first only a memory cell contact hole is selectively formed and a silicon film is filled at the bottom. As a result, an optimum electrode structure can be each provided on an n type diffusion layer in the memory cell portion and an n type diffusion layer in the peripheral circuit portion.

Abstract: A field effect transistor includes a lower gate electrode, upper gate electrode, first, second, and third barrier films, and source and drain. The lower gate electrode is formed from silicon on a silicon substrate via a gate insulating film. The upper gate electrode is formed from copper above the lower gate electrode. The first barrier film has a conductivity capable of supplying to the lower gate electrode a current enough to drive a channel portion, covers the lower surface of the upper gate electrode, and impedes diffusion of copper. The second barrier film has a lower end in contact with the first barrier film, covers the side surfaces of the upper gate electrode, and impedes diffusion of copper. The third barrier film has an end portion in contact with the second barrier film, covers the upper surface of the upper gate electrode, and impedes diffusion of copper. The source and drain are formed in the silicon substrate to sandwich a region under the lower gate electrode.

Abstract: There is provided a semiconductor device including (a) a semiconductor substrate, (b) a capacity device, (c) an interlayer insulating layer formed between the semiconductor substrate and the capacity device for electrically isolating them with each other, the interlayer insulating layer being formed below the capacity device with a contact hole therethrough, (d) a contact plug composed of an electrically conductive material and formed in the contact hole, (e) a first film composed of a first material through which hydrogen is not allowed to pass, and formed between the interlayer insulating layer and capacity device, (f) a second film composed of a second material through which hydrogen is not allowed to pass, and formed on an inner wall of the contact hole, (g) a third film composed of a third material through which hydrogen is not allowed to pass, and formed to cover an upper surface of the capacity device therewith, and (h) a fourth film composed of a fourth material through which hydrogen is not allowed t

Abstract: There is provided a semiconductor device including (a) a semiconductor substrate, (b) a capacity device, (c) an interlayer insulating layer formed between the semiconductor substrate and the capacity device for electrically isolating them with each other, the interlayer insulating layer being formed below the capacity device with a contact hole therethrough, (d) a contact plug composed of an electrically conductive material and formed in the contact hole, (e) a first film composed of a first material through which hydrogen is not allowed to pass, and formed between the interlayer insulating layer and capacity device, (f) a second film composed of a second material through which hydrogen is not allowed to pass, and formed on an inner wall of the contact hole, (g) a third film composed of a third material through which hydrogen is not allowed to pass, and formed to cover an upper surface of the capacity device therewith, and (h) a fourth film composed of a fourth material through which hydrogen is not allowed t

Abstract: The interval between gate electrodes in a memory cell portion and the interval between gate electrodes in a peripheral circuit portion are set so as to have a relation with the widths of sidewall insulating films of the gate electrodes. Using an etching stopper film, first only a memory cell contact hole is selectively formed and a silicon film is filled at the bottom. As a result, an optimum electrode structure can be each provided on an n type diffusion layer in the memory cell portion and an n type diffusion layer in the peripheral circuit portion.

Abstract: The present invention provides a structure for a semiconductor device, capable of eliminating the generation of defective products due to poor connection. In the present semiconductor device, an n-type high concentration diffusion layer 2 is selectively formed on the P-type silicon substrate 1, and on the diffusion layer 2, a silicon oxide film 3 is formed as a first interlayer insulating film 3. A silicon plug 4 is disposed on the n-type high concentration diffusion layer 2. On the top end surface of the polysilicon plug 4, a silicide pad 5 is formed in a self-aligning manner such that the width of the silicide pad 5 is larger than that of the polysilicon plug 4. A second interlayer insulating film is formed so as to cover the first interlayer insulating film 3 and the silicide pad 5, and a tungsten plug 7 is disposed on the silicide pad 5. On the second interlayer insulating film, wiring 8, made of an aluminum-copper alloy and connected to the tungsten plug, is formed.

Abstract: There is provided a semiconductor device including (a) a semiconductor substrate, (b) a capacity device, (c) an interlayer insulating layer formed between the semiconductor substrate and the capacity device for electrically isolating them with each other, the interlayer insulating layer being formed below the capacity device with a contact hole therethrough, (d) a contact plug composed of an electrically conductive material and formed in the contact hole, (e) a first film composed of a first material through which hydrogen is not allowed to pass, and formed between the interlayer insulating layer and capacity device, (f) a second film composed of a second material through which hydrogen is not allowed to pass, and formed on an inner wall of the contact hole, (g) a third film composed of a third material through which hydrogen is not allowed to pass, and formed to cover an upper surface of the capacity device therewith, and (h) a fourth film composed of a fourth material through which hydrogen is not allowed t

Abstract: A capacitor is produced by forming, on an area of a lower electrode which is inside the outer periphery of the lower electrode, a ferroelectric layer which becomes a capacitive part, in a state that the side of the ferroelectric layer is covered by an insulator, and then forming an upper electrode on the ferroelectric layer.

Abstract: A thin film formation method includes the deposition step of forming a dielectric thin film consisting of many elements. In the deposition step, first- and second-layer thin films are deposited as lower and upper layers on an underlayer, and at least one of the thin films is crystallized to form the dielectric thin film. The first-layer thin film closer to the underlayer is deposited with a larger composition of at least one kind of constituent element of the thin film than stoichiometric composition to allow for diffusion outside the film.

Abstract: A method for manufacturing a nonvolatile semiconductor memory device comprises the steps of forming a ferroelectric capacitor, sputtering a first dielectric film on the ferroelectric capacitor, and depositing a second dielectric film on the first dielectric film by a CVD process using tetraethylorthosilicate as a source gas and ozone as an oxidizing agent at a temperature between 350 and 500.degree. C. The first dielectric film prevents hydrogen and water from being introduced into the ferroelectric film of the ferroelectric capacitor during and after the CVD process, thereby improving polarization, leakage current and dielectric breakdown characteristics of the ferroelectric capacitor.