Patents by Inventor Takeshi Aoki

Takeshi Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11453229
    Abstract: A recording apparatus includes: an apparatus body that includes a recorder that performs recording on a medium; an opening-and-closing member that is able to be opened away from and closed toward the apparatus body; a unit module that is detachably attached to an attachment portion configured to become exposed by opening the opening-and-closing member, and constitutes a part of a first medium transportation path when attached to the attachment portion; a second medium transportation path that is provided above the first medium transportation path; and a path forming member that is located above the attachment portion and forms a part of the second medium transportation path; wherein the path forming member is retracted from the second medium transportation path and advances onto the opening-and-closing trajectory of the opening-and-closing member when the unit module is detached from the attachment portion.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: September 27, 2022
    Assignee: Seiko Epson Corporation
    Inventor: Takeshi Aoki
  • Publication number: 20220293931
    Abstract: This positive electrode active material for nonaqueous electrolyte secondary batteries comprises a lithium-transition metal composite oxide and a surface modification layer. The lithium transition metal composite oxide contains at least Al and 80 mol % or more Ni with reference to the total number of moles of metal elements excluding Li, and the surface modification layer contains at least Sr and is formed on the surface of primary particles of the lithium-transition metal composite oxide.
    Type: Application
    Filed: July 28, 2020
    Publication date: September 15, 2022
    Applicants: Panasonic Corporation, SANYO Electric Co., Ltd.
    Inventors: Katsuya Inoue, Takeshi Ogasawara, Yoshinori Aoki, Shun Nomura
  • Publication number: 20220294402
    Abstract: A novel comparison circuit, a novel amplifier circuit, a novel battery control circuit, a novel battery protection circuit, a power storage device, a semiconductor device, an electric device, and the like are provided. In a semiconductor device, one of a source and a drain of a first transistor is electrically connected to one of a source and a drain of a second transistor and one of a source and a drain of a third transistor; the other of the source and the drain of the third transistor is electrically connected to a first output terminal; and the other of the source and the drain of the second transistor is electrically connected to a second output terminal.
    Type: Application
    Filed: August 11, 2020
    Publication date: September 15, 2022
    Inventors: Kei TAKAHASHI, Takeshi AOKI, Munehiro KOZUMA, Takayuki IKEDA
  • Publication number: 20220276838
    Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a plurality of operation circuits that can switch different kinds of operation processing; a plurality of switch circuits that can switch a connection state between the operation circuits; and a controller. The operation circuit includes a first memory that stores data corresponding to a weight parameter used in the plurality of kinds of operation processing. The operation circuit executes a product-sum operation by switching weight data in accordance with a context. The switch circuit includes a second memory that stores data for switching a plurality of connection states in response to switching of a second context signal. The controller generates a second context signal on the basis of a first context signal. The amount of data stored in the second memory can be smaller than the amount of data stored in the first memory in the operation circuit.
    Type: Application
    Filed: April 8, 2022
    Publication date: September 1, 2022
    Inventors: Munehiro KOZUMA, Takeshi AOKI, Seiichi YONEDA, Yoshiyuki KUROKAWA
  • Publication number: 20220276839
    Abstract: A semiconductor device includes a CPU and an accelerator that includes a first memory circuit, a driver circuit, and a product-sum operation circuit. The first memory circuit includes a first data retention portion, a second data retention portion, and a data reading portion. The first data retention portion, the second data retention portion, and the data reading portion each include a first transistor. The first transistor contains a metal oxide in a channel formation region. First data stored in the first data retention portion and second data stored in the second data retention portion are each weight data input to the product-sum operation circuit. The product-sum operation circuit has a function of performing product-sum operation of the weight data and input data input through the driver circuit. The product-sum operation circuit and the driver circuit each include a second transistor. The second transistor contains silicon in a channel formation region.
    Type: Application
    Filed: September 18, 2020
    Publication date: September 1, 2022
    Inventors: Takahiko ISHIZU, Takeshi AOKI, Kazuma FURUTANI, Takayuki IKEDA, Shunpei YAMAZAKI
  • Publication number: 20220276834
    Abstract: A semiconductor device which can efficiently perform reading of a weight coefficient and a product-sum operation is provided. The semiconductor device includes a product-sum operation circuit and a memory device. The product-sum operation circuit is formed using transistors formed on a semiconductor substrate, and a memory cell of the memory device is formed using an OS transistor provided to be stacked above the semiconductor substrate. The semiconductor device includes a plurality of product-sum operation units where the product-sum operation circuit and the memory cell of the memory device are electrically connected to each other. In each of the product-sum operation units, a weight coefficient stored in the memory cell can be read and a product-sum operation can be performed.
    Type: Application
    Filed: June 29, 2020
    Publication date: September 1, 2022
    Inventors: Takeshi AOKI, Yoshiyuki KUROKAWA, Munehiro KOZUMA, Takuro KANEMURA
  • Patent number: 11430820
    Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: August 30, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura
  • Publication number: 20220262953
    Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a CPU and an accelerator. The accelerator includes a first memory circuit and an arithmetic circuit. The first memory circuit includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The arithmetic circuit includes a second transistor. The second transistor includes a semiconductor layer containing silicon in a channel formation region. The first transistor and the second transistor are provided to be stacked. The CPU includes a CPU core including a flip-flop provided with a backup circuit. The backup circuit includes a third transistor. The third transistor includes a semiconductor layer containing a metal oxide in a channel formation region.
    Type: Application
    Filed: July 27, 2020
    Publication date: August 18, 2022
    Inventors: Munehiro KOZUMA, Takahiko ISHIZU, Takeshi AOKI, Masashi FUJITA, Kazuma FURUTANI, Kousuke SASAKI
  • Publication number: 20220254401
    Abstract: A semiconductor device resistant to a high temperature with low power consumption is provided. The semiconductor device includes a first and a second circuit, a first and a second cell, and a first and a second wiring. The first cell includes a first transistor, and the second cell includes a second transistor. The first and the second transistor operate in a subthreshold region. The first cell is electrically connected to the first circuit through the first wiring, the first cell is electrically connected to the second circuit through the second wiring, and the second cell is electrically connected to the second circuit through the second wiring. The first cell sets a current flowing through the first transistor to a first current and the second cell sets a current flowing through the second transistor to a second current. At this time, a potential corresponding to the second current is input from the second wiring to the first cell.
    Type: Application
    Filed: June 8, 2020
    Publication date: August 11, 2022
    Inventors: Yoshiyuki KUROKAWA, Munehiro KOZUMA, Takeshi AOKI
  • Publication number: 20220255074
    Abstract: Provided is a cathode active material for a non-aqueous-electrolyte secondary battery, the cathode active material containing a lithium composite oxide that has a layered structure containing a Li layer and that is represented by general formula LiaNi?Al?Co?M?SrxO2-w (in the formula, 0.95<a<1.05, 0.85???0.95, 0<??0.08, 0???0.1, 0???0.15, 0<x?0.015, 0?w<0.05, ?+?+?+?=1, and M is at least one type of element selected from Mn, Fe, Ti, Si, Nb, Zr, Mo, and Zn), wherein the proportions of metal elements present in the Li layer excluding Li are in the range of 1-2.5 mol % with respect to the total molar quantity of metal elements in the lithium composite oxide excluding Li.
    Type: Application
    Filed: June 23, 2020
    Publication date: August 11, 2022
    Applicants: Panasonic Corporation, SANYO Electric Co., Ltd.
    Inventors: Yoshinori Aoki, Shun Nomura, Takeshi Ogasawara
  • Patent number: 11406903
    Abstract: An information processing device includes a receiving section configured to receive an input of a usage purpose of the information processing device from a user, an identifying section configured to identify a procedure including one or more steps necessary for realizing the usage purpose, a first screen generating section configured to generate an operating screen for completing one step in the identified procedure, and a second screen generating section configured to generate an information screen including information regarding the identified procedure.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: August 9, 2022
    Assignee: Sony Interactive Entertainment Inc.
    Inventors: You Asakura, Shuji Hiramatsu, Daisuke Kawamura, Wataru Kaneko, Takashi Hatakeda, Takeshi Nakagawa, Shigeru Enomoto, Toru Yamamoto, Satoshi Kobayashi, Koichi Aoki
  • Publication number: 20220243872
    Abstract: A fusible plug for a high pressure gas cylinder includes a communication hole filled with a low melting point alloy, a porous metal sintered body is press-fitted in at least a part of the communication hole in a length direction, all or a part of the porous metal sintered body is impregnated with the low melting point alloy to solidify and composite the low melting point alloy. It is preferable that: the low melting point alloy has a melting point of 110° C.; the porous metal sintered body to be press-fitted is a porous metal sintered body having pores with an area ratio of 30% or more and 50% or less and having pores with a diameter exceeding 5 ?m among the pores of 80% or more in terms of area ratio to all the pores; and the porous metal sintered body is a porous austenitic stainless steel sintered body.
    Type: Application
    Filed: January 28, 2022
    Publication date: August 4, 2022
    Applicants: NIPPON PISTON RING CO., LTD., JTEKT CORPORATION
    Inventors: Hiroshi TAKIGUCHI, Atsuya AOKI, Kazushi NUMAZAKI, Takeshi TAKAHASHI, Natsuki IWAMOTO, Yudai WATANABE
  • Publication number: 20220219654
    Abstract: A brake operation portion that allows a manual brake operation is included in a vehicle cabin, the brake operation portion includes a grip portion, and an elbow rest member is provided at, in the vehicle rear side of the grip portion, a position on which an elbow of a driver can abut in a state in which the driver grips the grip portion so as to be capable of operating the grip portion. Thus, even a physically disabled driver may freely perform a driving operation and easily manually perform a delicate brake operation.
    Type: Application
    Filed: December 20, 2021
    Publication date: July 14, 2022
    Applicant: Mazda Motor Corporation
    Inventors: Ryo OYAMA, Takeshi SASAKI, Masaaki AOKI
  • Publication number: 20220224079
    Abstract: A vertical-cavity surface-emitting laser includes a substrate having a main surface, a first lower distributed Bragg reflector that extends to an edge of the main surface, a III-V compound semiconductor layer disposed on the first lower distributed Bragg reflector, a second lower distributed Bragg reflector disposed on the III-V compound semiconductor layer, an active layer disposed above the second lower distributed Bragg reflector and an upper distributed Bragg reflector disposed on the active layer. The first lower distributed Bragg reflector includes a first layer and a second layer that are alternately arranged. The upper distributed Bragg reflector includes a third layer and a fourth layer that are alternately arranged. The III-V compound semiconductor layer is free of aluminum or has an aluminum composition less than an aluminum composition of the third layer. The first layer has an aluminum composition greater than the aluminum composition of the third layer.
    Type: Application
    Filed: December 1, 2021
    Publication date: July 14, 2022
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Takeshi AOKI
  • Publication number: 20220208245
    Abstract: A semiconductor device with reduced power consumption is provided. The semiconductor device includes a transmitter unit, a receiver unit, a bias-outputting unit, and a controller unit. The bias-outputting unit has a plurality of memory units. The plurality of memory units each retains information to determine transmission power. The receiver unit receives a request signal transmitted from a base station and supplies it to the controller unit. The controller unit selects one of the plurality of memory units according to the request signal. The memory unit has an OS transistor and retains information when power supply is stopped.
    Type: Application
    Filed: April 13, 2020
    Publication date: June 30, 2022
    Inventors: Munehiro KOZUMA, Takayuki IKEDA, Kei TAKAHASHI, Takeshi AOKI
  • Publication number: 20220209229
    Abstract: This positive electrode for a nonaqueous electrolyte secondary battery is provided with: a positive electrode active material including lithium composite oxide particles containing not less than 80 mol % but less than 100 mol % of Ni with respect to the total number of moles of metal elements other than Li; and a conductive material, wherein the lithium composite oxide particles include particles each having a step-like structure with three or more stacked flat surfaces having an outer edge length of 1 ?m or more, and the average particle size of the conductive material is 30 nm or less.
    Type: Application
    Filed: February 5, 2020
    Publication date: June 30, 2022
    Applicant: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Manabu Takijiri, Takeshi Ogasawara, Motoharu Saito, Yoshinori Aoki
  • Publication number: 20220190398
    Abstract: A semiconductor device with reduced power consumption is provided. With three transistors, potentials of two nodes are switched and a voltage is detected. One of a source and a drain of a first transistor is electrically connected to a first terminal. The other of the source and the drain of the first transistor is electrically connected to a non-inverting input of a comparator through a first node. One of a source and a drain of a second transistor is electrically connected to a second terminal. The other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of a third transistor through a second node. The other of the source and the drain of the third transistor is electrically connected to a third terminal. A first capacitor is provided between the first node and the second node. An inverting input of the comparator is electrically connected to a fourth terminal. An output of the comparator is electrically connected to a fifth terminal.
    Type: Application
    Filed: March 16, 2020
    Publication date: June 16, 2022
    Inventors: Takayuki IKEDA, Takeshi AOKI, Munehiro KOZUMA, Kei TAKAHASHI, Shunpei YAMAZAKI
  • Patent number: 11358398
    Abstract: There is provided a print control device that causes a printing device to perform printing, the print control device including: a specifying section that specifies a print target from a captured image captured by an image capturing sensor; a display section that displays, on a display, a screen in which a trimmed image is superimposed on the captured image, the trimmed image being obtained by trimming a preview image of original print data in accordance with the print target; a setting receiving section that receives a setting of a relative position of the preview image with respect to the print target; a print instruction receiving section that receives a print instruction at the relative position; and a control section that causes the printing device to perform printing on the print target based on the original print data and the relative position according to the print instruction.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: June 14, 2022
    Assignee: Seiko Epson Corporation
    Inventors: Hiroaki Nakanishi, Ikuo Masujima, Kiyokazu Kamijo, Kei Miyazawa, Takahiro Otani, Junko Yamamoto, Takeshi Aoki, Akinobu Miyasaka, Shiori Naruse
  • Publication number: 20220180159
    Abstract: A system that creates a net list from a circuit diagram or a document showing a circuit structure is provided. The system is an AI system including a first electronic device. The first electronic device includes an input/output interface, a control portion, and a first conversion portion. The input/output interface is electrically connected to the control portion, and the first conversion portion is electrically connected to the control portion. The input/output interface has a function of transmitting input data generated by a user's operation to the control portion, and the control portion has a function of transmitting the input data to the first conversion portion. Note that the input data is a circuit diagram illustrating a circuit structure or a document file showing the circuit structure. The first conversion portion includes a circuit where a neural network is formed, and the input data is converted to a net list with the use of the neural network of the first conversion portion.
    Type: Application
    Filed: January 24, 2020
    Publication date: June 9, 2022
    Inventors: Hajime KIMURA, Rihito WADA, Masayuki KIMURA, Yoshiyuki KUROKAWA, Takeshi AOKI
  • Publication number: 20220173737
    Abstract: A semiconductor device is provided; the semiconductor device includes unipolar transistors. A steady-state current does not flow in the semiconductor device. The semiconductor device uses a high-level potential and a low-level potential to express a high level and a low level, respectively. The semiconductor device includes unipolar transistors, a capacitor, first and second input terminals, and an output terminal. To the second input terminal, a signal is input whose logic is inverted from the logic of a signal input to the first input terminal. The semiconductor device has a circuit structure called bootstrap in which two unipolar transistors are connected in series between the high-level potential and the low-level potential and a capacitor is provided between an output terminal and a gate of one of the two transistors. A delay is caused between the gate of the transistor and the signal output from the output terminal, whereby the bootstrap can be certainly performed.
    Type: Application
    Filed: March 12, 2020
    Publication date: June 2, 2022
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki INOUE, Munehiro KOZUMA, Takeshi AOKI, Shuji FUKAI, Fumika AKASAWA, Sho NAGAO