Patents by Inventor Takeshi Asada
Takeshi Asada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11970562Abstract: A phase difference film composed of a resin containing a copolymer including polymerization units A and B, the phase difference film including a cylindrical phase separation structure that generates a structural birefringence, the phase separation structure including a phase (A) having the polymerization unit A as a main component and a phase (B) having the polymerization unit B as a main component, and the phase difference film satisfying the following condition (1) or (2). Condition (1): D(A)>D(B) and f(B)>0.5, and a direction giving a maximum refractive index among in-plane directions and an orientation direction of a cylinder in the phase separation structure are parallel to each other. Condition (2): D(A)>D(B) and f(A)>0.5, and a direction giving a maximum refractive index among in-plane directions and an orientation direction of a cylinder in the phase separation structure are orthogonal to each other.Type: GrantFiled: March 18, 2019Date of Patent: April 30, 2024Assignee: ZEON CORPORATIONInventors: Takeshi Asada, Hironari Sudeji, Kensaku Fujii, Yusuke Yasu, Hiroya Nishioka
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Method of manufacturing MOSFET having a semiconductor base substrate with a super junction structure
Patent number: 11843048Abstract: A MOSFET includes: a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure; and a gate electrode formed by way of a gate insulation film. Assuming a region of the semiconductor base substrate which provides a main operation of the MOSFET as an active region, a region of the semiconductor base substrate maintaining a withstand voltage of the MOSFET as an outer peripheral region, and a region of the semiconductor base substrate disposed between the active region and the outer peripheral region as an active connecting region, out of the active region, the active connecting region, and the outer peripheral region of the semiconductor base substrate, the crystal defects are formed only in the active region and the active connecting region.Type: GrantFiled: April 22, 2022Date of Patent: December 12, 2023Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Daisuke Arai, Mizue Kitada, Takeshi Asada, Noriaki Suzuki, Koichi Murakami -
Publication number: 20230373916Abstract: Provided is a curable compound product having excellent storage stability that is rapidly cured upon heating to form a cured product having ultra-high heat resistance. The curable compound product according to the present disclosure has the following characteristics (a) to (e): (a) A number average molecular weight (calibrated with polystyrene standard) is from 1000 to 15000. (b) A proportion of a structure derived from an aromatic ring in a total amount of the curable compound product is 50 wt. % or greater. (c) Solvent solubility at 23° C. is 1 g/100 g or greater. (d) The glass transition temperature is from 80 to 230° C. (e) A viscosity (?0) of a 20 wt. % NMP solution obtained by subjecting the curable compound product to a reduced-pressure drying process and then dissolving the reduced-pressure-dried curable compound product in NMP, and a viscosity (?10) of the 20 wt. % NMP solution after being left to stand for 10 days in a desiccator maintained at 23° C. satisfy the Equation (E): ?10/?0<2(E).Type: ApplicationFiled: October 5, 2021Publication date: November 23, 2023Applicant: DAICEL CORPORATIONInventors: Yoshimichi OKANO, Takeshi ASADA
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Publication number: 20230241829Abstract: A method for producing a phase difference film is provided. The phase difference film includes an orientation layer formed of a resin C having a negative intrinsic birefringence value. The resin C contains a block copolymer having a block (A) including as a main component a polymerization unit A having a negative intrinsic birefringence value and a block (B) including as a main component a polymerization unit B, and a weight fraction of the block (A) therein being 50% by weight or more and 90% by weight or less. The phase difference film has an NZ factor of greater than 0 and smaller than 1. The method comprising: forming a single layer film of the resin C; and causing phase separation of the resin C in the film, which includes a step of applying to the film a stress along a thickness direction thereof.Type: ApplicationFiled: February 21, 2023Publication date: August 3, 2023Applicant: ZEON CORPORATIONInventors: Takeshi ASADA, Hironari SUDEJI, Kensaku FUJII
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Publication number: 20230202090Abstract: A method for producing a phase difference film is provided. The phase difference film consisting of a resin C contains a copolymer P containing a polymerization unit A and a polymerization unit B, and includes a phase separation structure that exhibits a structural birefringence. The phase separation structure includes a phase including as a main component the polymerization unit A and another phase including as a main component the polymerization unit B. The phase difference film has an NZ factor of greater than 0 and smaller than 1. The method comprises: forming a single layer film of a resin C; and causing phase separation of the resin C in the film, which includes a step of applying to the film a stress along a thickness direction thereof.Type: ApplicationFiled: February 22, 2023Publication date: June 29, 2023Applicant: ZEON CORPORATIONInventor: Takeshi ASADA
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Publication number: 20220246755Abstract: A MOSFET includes: a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure; and a gate electrode formed by way of a gate insulation film. Assuming a region of the semiconductor base substrate which provides a main operation of the MOSFET as an active region, a region of the semiconductor base substrate maintaining a withstand voltage of the MOSFET as an outer peripheral region, and a region of the semiconductor base substrate disposed between the active region and the outer peripheral region as an active connecting region, out of the active region, the active connecting region, and the outer peripheral region of the semiconductor base substrate, the crystal defects are formed only in the active region and the active connecting region.Type: ApplicationFiled: April 22, 2022Publication date: August 4, 2022Inventors: Daisuke ARAI, Mizue KITADA, Takeshi ASADA, Noriaki SUZUKI, Koichi MURAKAMI
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Patent number: 11342452Abstract: A MOSFET includes: a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure; and a gate electrode formed by way of a gate insulation film. Assuming a region of the semiconductor base substrate which provides a main operation of the MOSFET as an active region, a region of the semiconductor base substrate maintaining a withstand voltage of the MOSFET as an outer peripheral region, and a region of the semiconductor base substrate disposed between the active region and the outer peripheral region as an active connecting region, out of the active region, the active connecting region, and the outer peripheral region of the semiconductor base substrate, the crystal defects are formed only in the active region and the active connecting region.Type: GrantFiled: December 27, 2017Date of Patent: May 24, 2022Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Daisuke Arai, Mizue Kitada, Takeshi Asada, Noriaki Suzuki, Koichi Murakami
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Publication number: 20210032396Abstract: A phase difference film composed of a resin C containing a copolymer P including a polymerization unit A and a polymerization unit B, the phase difference film including a lamellar phase separation structure that generates a structural birefringence, the phase separation structure including a phase (A) having the polymerization unit A as a main component and a phase (B) having the polymerization unit B as a main component, and the phase difference film satisfying the formulae (1A): f(A)>0.5 and (2):D(A)>D(B), or the formulae (1B): f(B)>0.5 and (2). f(A) represents a total weight ratio of the polymerization unit A in the copolymer P, f(B) represents a total weight ratio of the polymerization unit B in the copolymer P, D(A)=ReA(450)/ReA(550), D(B)=ReB(450)/ReB(550), and ReA(450), ReA(550), ReB(450) and ReB(550) are as defined in the description.Type: ApplicationFiled: March 18, 2019Publication date: February 4, 2021Applicant: ZEON CORPORATIONInventors: Takeshi ASADA, Hironari SUDEJI, Kensaku FUJII, Yusuke YASU, Hiroya NISHIOKA
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Publication number: 20210009744Abstract: A phase difference film composed of a resin containing a copolymer including polymerization units A and B, the phase difference film including a cylindrical phase separation structure that generates a structural birefringence, the phase separation structure including a phase (A) having the polymerization unit A as a main component and a phase (B) having the polymerization unit B as a main component, and the phase difference film satisfying the following condition (1) or (2). Condition (1): D(A)>D(B) and f(B)>0.5, and a direction giving a maximum refractive index among in-plane directions and an orientation direction of a cylinder in the phase separation structure are parallel to each other. Condition (2): D(A)>D(B) and f(A)>0.5, and a direction giving a maximum refractive index among in-plane directions and an orientation direction of a cylinder in the phase separation structure are orthogonal to each other.Type: ApplicationFiled: March 18, 2019Publication date: January 14, 2021Applicant: ZEON CORPORATIONInventors: Takeshi ASADA, Hironari SUDEJI, Kensaku FUJII, Yusuke YASU, Hiroya NISHIOKA
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Patent number: 10818496Abstract: A MOSFET includes: a semiconductor base substrate having n-type column regions and p-type column regions, the n-type column regions and the p-type column regions forming a super junction structure; and a gate electrode which is formed on a first main surface side of the semiconductor base substrate by way of a gate insulation film, wherein crystal defects whose density is increased locally as viewed along a depth direction are formed in the n-type column regions and the p-type column regions, using the first main surface as a reference and assuming a depth to a deepest portion of the super junction structure as Dp, a depth at which density of the crystal defects exhibits a maximum value as Dd, and a half value width of density distribution of the crystal defects as W, a relationship of 0.25Dp?Dd<0.95Dp and a relationship of 0.05Dp<W<0.5Dp are satisfied.Type: GrantFiled: July 26, 2019Date of Patent: October 27, 2020Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Daisuke Arai, Mizue Kitada, Takeshi Asada, Noriaki Suzuki, Koichi Murakami
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Publication number: 20200255573Abstract: A phase difference film solely consisting essentially of a single species of copolymer P containing a polymerization unit A and a polymerization unit B, the phase difference film having a phase separation structure that exhibits a structural birefringence, and the phase difference film having an NZ factor of greater than 0 and smaller than 1; and the production method therefor. Preferably, the phase separation structure has a form of any of lamella, cylinder and spheroid, and the distance between phases in the phase separation structure is 200 nm or less.Type: ApplicationFiled: May 18, 2018Publication date: August 13, 2020Applicant: ZEON CORPORATIONInventor: Takeshi ASADA
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Publication number: 20200209452Abstract: A phase difference film including an orientation layer formed of a resin C having a negative intrinsic birefringence value, wherein the resin C contains a block copolymer having a block (A) including as a main component a polymerization unit A having a negative intrinsic birefringence value and a block (B) including as a main component a polymerization unit B, and a weight fraction of the block (A) therein being 50% by weight or more and 90% by weight or less, and the phase difference film has an NZ factor of greater than 0 and smaller than 1; and the production method thereof. Preferably, in the orientation layer, the resin C exhibits a phase separation structure, and a distance between phases in the phase separation structure is 200 nm or less.Type: ApplicationFiled: May 18, 2018Publication date: July 2, 2020Applicant: ZEON CORPORATIONInventors: Takeshi ASADA, Hironari SUDEJI, Kensaku FUJII
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Patent number: 10700191Abstract: A MOSFET used in a power conversion circuit including a reactor, a power source, the MOSFET, and a rectifier element, includes a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure, the n-type column region and the p-type column region are formed such that a total amount of a dopant in the p-type column region is set higher than a total amount of a dopant in the n-type column region, and the MOSFET is configured to be operated in response to turning on of the MOSFET such that at a center of the n-type column region as viewed in a plan view, a low electric field region having lower field intensity than areas of the n-type column region other than the center of the n-type column region appears.Type: GrantFiled: September 16, 2016Date of Patent: June 30, 2020Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Daisuke Arai, Shigeru Hisada, Mizue Kitada, Takeshi Asada
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Publication number: 20200183067Abstract: A phase difference film consisting of a resin C contains a copolymer P containing a polymerization unit A and a polymerization unit B, the phase difference film including a phase separation structure that exhibits a structural birefringence, the phase separation structure including a phase including as a main component the polymerization unit A and another phase including as a main component the polymerization unit B, and the phase difference film having an NZ factor of greater than 0 and smaller than 1; and a production method therefor. Preferably, the phase separation structure has a form of any of lamella, cylinder and spheroid, and the distance between phases in the phase separation structure is 200 nm or less.Type: ApplicationFiled: May 18, 2018Publication date: June 11, 2020Applicant: ZEON CORPORATIONInventor: Takeshi ASADA
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Publication number: 20200119187Abstract: A MOSFET includes: a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure; and a gate electrode formed by way of a gate insulation film. Assuming a region of the semiconductor base substrate which provides a main operation of the MOSFET as an active region, a region of the semiconductor base substrate maintaining a withstand voltage of the MOSFET as an outer peripheral region, and a region of the semiconductor base substrate disposed between the active region and the outer peripheral region as an active connecting region, out of the active region, the active connecting region, and the outer peripheral region of the semiconductor base substrate, the crystal defects are formed only in the active region and the active connecting region.Type: ApplicationFiled: December 27, 2017Publication date: April 16, 2020Inventors: Daisuke ARAI, Mizue KITADA, Takeshi ASADA, Noriaki SUZUKI, Koichi MURAKAMI
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Publication number: 20200020536Abstract: A MOSFET includes: a semiconductor base substrate having n-type column regions and p-type column regions, the n-type column regions and the p-type column regions forming a super junction structure; and a gate electrode which is formed on a first main surface side of the semiconductor base substrate by way of a gate insulation film, wherein crystal defects whose density is increased locally as viewed along a depth direction are formed in the n-type column regions and the p-type column regions, using the first main surface as a reference and assuming a depth to a deepest portion of the super junction structure as Dp, a depth at which density of the crystal defects exhibits a maximum value as Dd, and a half value width of density distribution of the crystal defects as W, a relationship of 0.25Dp?Dd<0.95Dp and a relationship of 0.05Dp<W<0.5Dp are satisfied.Type: ApplicationFiled: July 26, 2019Publication date: January 16, 2020Inventors: Daisuke ARAI, Mizue KITADA, Takeshi ASADA, Noriaki SUZUKI, Koichi Murakami
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Patent number: 10475917Abstract: A MOSFET includes a semiconductor base substrate where a super junction structure is formed of an n-type column region and a p-type column region. A total amount of a dopant in the n-type column region is set to a value greater than a total amount of a dopant in the p-type column region. The MOSFET is configured to be operated during a period from a point of time when a drain current starts to decrease to a point of time when the drain current becomes 0 for the first time in response to turning off of the MOSFET such that a first period during which the drain current is decreased, a second period during which the drain current is increased or the drain current becomes constant, and a third period during which the drain current is decreased again occur in this order.Type: GrantFiled: May 21, 2018Date of Patent: November 12, 2019Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Daisuke Arai, Shigeru Hisada, Mizue Kitada, Takeshi Asada
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Patent number: 10468518Abstract: A power semiconductor device of the present invention includes: a semiconductor base body which has a super junction structure formed of a plurality of first conductive-type columnar regions and a plurality of second conductive-type columnar regions; a plurality of trenches; gate insulation films; gate electrodes; an interlayer insulation film; contact holes formed such that two or more contact holes are formed between two trenches disposed adjacently to each other; metal plugs formed by filling the inside of the contact holes with metal; and an electrode, wherein a first conductive-type high concentration diffusion region is formed only between the trench and the metal plug disposed closest to the trench between each two trenches disposed adjacently to each other. According to the power semiconductor device of the present invention, it is possible to provide a power semiconductor device which satisfies a demand for reduction in cost and downsizing of electronic equipment, and has a large breakdown strength.Type: GrantFiled: January 16, 2017Date of Patent: November 5, 2019Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Mizue Kitada, Takeshi Asada, Takeshi Yamaguchi, Noriaki Suzuki, Daisuke Arai
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Patent number: 10439056Abstract: A power semiconductor device according to the present invention has a super junction structure, and includes a low-resistance semiconductor layer, an n?-type column region, p?-type column regions, a base region, trenches, gate insulation films, gate electrodes, source regions, interlayer insulation films, contact holes, metal plugs, p+-type diffusion regions, a source electrode and a gate pad electrode. An active element part includes an n?-type column region between a predetermined p?-type column region disposed closest to a gate pad part and a predetermined n?-type column region disposed closest to the gate pad part among the n?-type column regions which are in contact with the trenches. The present invention provides a power semiconductor device which can satisfy a demand for reduction in cost and downsizing of electronic equipment, can lower ON resistance while maintaining a high withstand voltage, and can possess a large breakdown resistance.Type: GrantFiled: March 31, 2016Date of Patent: October 8, 2019Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Daisuke Arai, Mizue Kitada, Takeshi Asada, Takeshi Yamaguchi, Noriaki Suzuki
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Patent number: 10411141Abstract: A semiconductor device includes: a semiconductor base body where a second semiconductor layer is stacked on a first semiconductor layer, a trench is formed on a surface of the second semiconductor layer, and a third semiconductor layer which is formed of an epitaxial layer is formed in the inside of the trench; a first electrode; an interlayer insulation film which has a predetermined opening; and a second electrode, wherein metal is filled in the opening, the opening is disposed at a position avoiding a center portion of the third semiconductor layer, the second electrode is connected to the third semiconductor layer through the metal, and a surface of the center portion of the third semiconductor layer is covered by the interlayer insulation film.Type: GrantFiled: February 27, 2017Date of Patent: September 10, 2019Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Mizue Kitada, Takeshi Asada, Takeshi Yamaguchi, Noriaki Suzuki, Daisuke Arai