Abstract: This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.

Abstract: According to this invention, there is provided a NAND-type semiconductor storage device including a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a buried insulating film selectively formed between the semiconductor substrate and the semiconductor layer in a memory transistor formation region, diffusion layers formed on the semiconductor layer in the memory transistor formation region, floating body regions between the diffusion layers, a first insulating film formed on each of the floating body regions, a floating gate electrode formed on the first insulating film, a control electrode on a second insulating film formed on the floating gate electrode, and contact plugs connected to ones of the pairs of diffusion layers which are respectively located at ends of the memory transistor formation region, wherein the ones of the pairs of diffusion layers, which are located at the ends of the memory transistor formation region, are connected to the semiconductor substrate belo

Abstract: This disclosure concerns a method of manufacturing a semiconductor memory device comprising forming a plurality of trenches in a semiconductor substrate; forming a semiconductor layer provided on a cavity by connecting lower spaces of the trenches to one another and closing upper openings of the trenches in a heat treatment under a hydrogen atmosphere; etching the semiconductor layer in an isolation formation area; forming an insulating film on a side surface and a bottom surface of the semiconductor layer; filling the cavity under the semiconductor layer with an electrode material; and forming a memory element on the semiconductor layer.

Abstract: A semiconductor device includes a substrate having first and second regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in the second region and having an upper surface higher than an upper surface of the first insulating film, and a first semiconductor layer formed on the first insulating film with a space provided with respect to the first epitaxial layer, having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer and having a tapered surface faced to a side surface of the first epitaxial layer.

Abstract: In one embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a to-be-removed layer on a semiconductor substrate; forming a semiconductor layer on the to-be-removed layer; forming a trench that passes through the semiconductor layer to the to-be-removed layer in an SOI region; removing the to-be-removed layer by using the trench and creating a cavity; and forming an insulating film in the cavity

Abstract: According to this invention, there is provided a NAND-type semiconductor storage device including a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate, a buried insulating film selectively formed between the semiconductor substrate and the semiconductor layer in a memory transistor formation region, diffusion layers formed on the semiconductor layer in the memory transistor formation region, floating body regions between the diffusion layers, a first insulating film formed on each of the floating body regions, a floating gate electrode formed on the first insulating film, a control electrode on a second insulating film formed on the floating gate electrode, and contact plugs connected to ones of the pairs of diffusion layers which are respectively located at ends of the memory transistor formation region, wherein the ones of the pairs of diffusion layers, which are located at the ends of the memory transistor formation region, are connected to the semiconductor substrate belo

Abstract: A semiconductor device of one embodiment of the present invention includes a substrate; isolation layers, each of which is formed in a trench formed on the substrate and has an insulating film and a conductive layer; a semiconductor layer of a first conductivity type for storing signal charges, formed between the isolation layers and isolated from the conductive layers by the insulating films; a semiconductor layer of a second conductivity type, formed under the semiconductor layer of the first conductivity type; and a transistor having a gate insulator film formed on the semiconductor layer of the first conductivity type and a gate electrode formed on the gate insulator film.

Abstract: A silicide film is provided in diffusion regions formed in a semiconductor layer. The silicide film has a thickness substantially same as that of the semiconductor layer. The silicide film has the bottom located in the vicinity of an interface between the insulator film and the semiconductor layer.

Abstract: A method for forming a SOI substrate device having multiple buried oxide regions comprising the steps of; forming a thin buried oxide layer in a silicon-containing substrate, forming a mask with openings therein on the substrate, implanting oxygen into the substrate through the openings in the mask, forming a buried oxide region in the substrate and a thermal oxide layer at the substrate surface in the mask openings by annealing, exposing the regions of the substrate that were not thermally oxidized by removing the mask, planarizing the crystalline silicon surface of the substrate by thermally oxidizing the substrate surface, removing the oxide layer from the surface of the substrate, exposing a crystalline silicon surface that has no steps between different buried oxide regions of the substrate.

Abstract: According to the present invention, there is provided a semiconductor memory device having: a semiconductor layer of a first conductivity type formed above a semiconductor substrate via an embedded insulation film, a gate electrode formed above the semiconductor layer via a gate insulation film, a floating body region of a first conductivity type formed under the gate electrode in the semiconductor layer of a first conductivity type, which functions as a collector region of a first conductivity type, a source region of a second conductivity type and a drain region of a second conductivity type formed on both sides of the floating body region in the semiconductor layer, the drain region functioning as a base region of a second conductivity type, an emitter region of a first conductivity type formed in the semiconductor layer, adjacent to the side opposite to the side of the floating body region in the drain region, and silicide formed at least on the surface portion of the source region.

Abstract: The PROM area is adjacent to the normal memory cell area. The data writing (normal writing) and the data reading (normal reading) for normal memory cell areas and the data writing (redundant writing) for the PROM area are carried out from the side of the normal memory cell areas. The data reading (redundant reading) for the PROM area is carried out from the side of the PROM area. In the PROM area, the PROM cells having the same structure as that of the normal memory cells are connected to the redundant sub bit lines. In the redundant writing, in the select gate area, the redundant sub bit lines and main bit lines are connected. In the redundant reading, in the redundant gate area having the same layout as that of the select gate area, the redundant sub bit lines are connected to redundant bit lines.

Abstract: A semiconductor storage device, has a first conductive type semiconductor region formed on a semiconductor substrate, a plurality of second conductive type semiconductor regions formed separately from each other on the first conductive type semiconductor region, a plurality of MOSFETs each formed on the plurality of second conductive type semiconductor regions, and element isolating regions each formed between the adjacent second conductive type semiconductor regions, a bottom surface of which being located in the first conductive type semiconductor region, wherein the number of crystal defects per unit volume in the first conductive type semiconductor region is larger than the number of the crystal defects per unit volume in the second conductive type semiconductor regions.

Abstract: A semiconductor device includes a substrate having first and second regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in the second region and having an upper surface higher than an upper surface of the first insulating film, and a first semiconductor layer formed on the first insulating film with a space provided with respect to the first epitaxial layer, having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer and having a tapered surface faced to a side surface of the first epitaxial layer.

Abstract: An insulated gate type field effect transistor in a memory cell array is a transistor having a gate insulating film which is thicker than a gate insulating film of an insulated gate type field effect transistor in an array peripheral circuit. DRAM (Dynamic Random Access Memory) cell-based semiconductor memory device can be implemented which allows a burn-in test to be accurately performed without degrading sensing operation characteristics even under a low power supply voltage.

Abstract: A semiconductor device includes a substrate having first to fourth regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in the second region and having an upper surface higher than an upper surface of the first insulating film, a first semiconductor layer formed on the first insulating film with a space provided with respect to the first epitaxial layer and having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer, and an element isolation insulating film formed in the space and having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer and the upper surface of the first semiconductor layer.

Abstract: A semiconductor device includes a substrate having first to fourth regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in the second region and having an upper surface higher than an upper surface of the first insulating film, a first semiconductor layer formed on the first insulating film with a space provided with respect to the first epitaxial layer and having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer, and an element isolation insulating film formed in the space and having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer and the upper surface of the first semiconductor layer.

Abstract: An optical proximity effect correcting method in a semiconductor manufacturing process includes adding, detecting, judging, and deleting. The adding includes adding a first correcting region around a portion of a first design pattern. The portion faces a second design pattern. A first corrected design pattern includes the first correcting region and the first design pattern. The detecting includes detecting a space between the first corrected design pattern and the second design pattern. The judging includes judging whether the space is smaller than or equal to a predetermined value. The deleting includes deleting at least a portion of the first correcting region such that the space is larger than the predetermined value, when the space is smaller than or equal to the predetermined value.

Abstract: A semiconductor device includes a substrate having first to fourth regions, a first insulating film formed on the substrate in the first region, a first epitaxial layer formed on the substrate in the second region and having an upper surface higher than an upper surface of the first insulating film, a first semiconductor layer formed on the first insulating film with a space provided with respect to the first epitaxial layer and having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer, and an element isolation insulating film formed in the space and having an upper surface set at substantially the same height as the upper surface of the first epitaxial layer and the upper surface of the first semiconductor layer.

Abstract: A semiconductor device includes two sense amplifiers provided on a semiconductor substrate. Each of two sense amplifiers is formed of a pair of transistors. Two transistors are separated from each other by an element-isolating insulating portion provided on the semiconductor substrate. Therefore unlike the conventional, two transistors do not share the source region with each other, resulting in a semiconductor device with an improved sensitivity of a sense amplifier.

Abstract: In a semiconductor memory unit to which a plurality of different functions can be imparted by merely changing a portion of its production process, the improvement comprises: a plurality of data buses which include first data buses for use only in one of the functions and the remaining data buses for use in the one and the remainder of the functions; wherein when the semiconductor memory unit performs the remainder of the functions, the first data buses are utilized for the semiconductor memory unit.