Patents by Inventor Takeshi Harada

Takeshi Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230131341
    Abstract: There is provided a printing apparatus including: a first receptacle connector that couples a first external device and an arithmetic section; a second receptacle connector that couples a second external device and the arithmetic section; and a USB controller that causes the arithmetic section to function as the device or the host based on a first electric signal input from the first external device and a second electric signal input from the second external device, in which, when the first external device is coupled, the USB controller causes the arithmetic section to function as the device when the second external device that functions as the device is coupled, causes the arithmetic section to function as the device when the second external device that functions as the host is coupled, and causes the arithmetic section to function as the device when the second external device is not coupled.
    Type: Application
    Filed: October 24, 2022
    Publication date: April 27, 2023
    Inventor: Takeshi HARADA
  • Publication number: 20230105456
    Abstract: Systems and methods for inserting a single pore into a membrane under faradaic conditions are described herein. A stepped or ramped voltage waveform can be applied across the membranes of the cells of an array, where the voltage waveform starts at first voltage and increases in magnitude over a period of time to a second voltage. The voltage waveform has a polarity that maintains a first species of a redox couple in its current oxidation state. The first voltage is selected to be low enough to reduce the risk of damaging the membrane, while the rate of voltage increase is selected to provide sufficient time for the pores to insert into the membranes. Once a pore is inserted into the membrane, the voltage across the membrane rapidly drops, thereby reducing the risk of damaging the membrane even if the applied voltage between the electrodes is further increased.
    Type: Application
    Filed: December 9, 2022
    Publication date: April 6, 2023
    Inventors: Geoffrey BARRALL, Eric Takeshi HARADA, Jason David KOMADINA, J. William MANEY, JR., Charlotte YANG
  • Publication number: 20230063832
    Abstract: There are provided a flat plate; a substrate having a first side and a second side facing an inner surface of the flat plate; a first receptacle connector that is provided along the first side of the substrate and configured to be coupled to a first plug of a first cable via a first opening of the flat plate; and a second receptacle connector that is provided along the second side of the substrate and configured to be coupled to a second plug of a second cable via a second opening of the flat plate, a distance from the inner surface to the first side is shorter than a distance from the inner surface to the second side.
    Type: Application
    Filed: August 30, 2022
    Publication date: March 2, 2023
    Inventor: Takeshi HARADA
  • Publication number: 20230068350
    Abstract: There are provided a printing section that performs printing on a medium; a control section that controls drive of the printing section; a power supply connector that supplies electric power to the control section; a first receptacle connector that is electrically coupled to a first external device and configured to cause the first external device to communicate with the control section; and a second receptacle connector that is electrically coupled to a second external device and configured to cause the second external device to communicate with the control section, a plug of a USB-Type-C cable is configured to be physically inserted into the second receptacle connector, the plug is configured not to be physically inserted into the power supply connector, and the power supply connector is arranged between the first receptacle connector and the second receptacle connector.
    Type: Application
    Filed: August 29, 2022
    Publication date: March 2, 2023
    Inventor: Takeshi HARADA
  • Publication number: 20230062398
    Abstract: There are provided a substrate; a main body case; and a first locking member and a second locking member for fixing the substrate and the main body case, the substrate includes a first receptacle connector configured to be coupled to a first plug of a first cable, a second receptacle connector configured to be coupled to a second plug of a second cable, a first coil that supplies electric power to the first receptacle connector, and a second coil that supplies electric power to the second receptacle connector, a distance from the first locking member to the first coil is shorter than a distance from the first locking member to the first receptacle connector, and a distance from the second locking member to the second coil is shorter than a distance from the second locking member to the second receptacle connector.
    Type: Application
    Filed: August 30, 2022
    Publication date: March 2, 2023
    Inventor: Takeshi HARADA
  • Publication number: 20230061909
    Abstract: There are provided a printing section; a control section; a power supply connector; a first receptacle connector that is electrically coupled to a first external device and configured to cause the first external device to communicate with the control section; a second receptacle connector that is electrically coupled to a second external device and configured to cause the second external device to communicate with the control section; and a third receptacle connector that is electrically coupled to a third external device and configured to cause the third external device to communicate with the control section, a first plug and a second plug are configured to be physically inserted into the third receptacle connector, the first plug and the second plug are configured not to be physically inserted into the power supply connector, and the first receptacle connector and the second receptacle connector are arranged adjacent to each other.
    Type: Application
    Filed: August 29, 2022
    Publication date: March 2, 2023
    Inventor: Takeshi HARADA
  • Publication number: 20230063866
    Abstract: There are provided a printing section that performs printing on a medium; a control section that controls drive of the printing section; a power supply connector that supplies electric power to the control section; a first receptacle connector that is electrically coupled to a first external device; and a second receptacle connector that is electrically coupled to a second external device, a plug of a USB-Type-C cable is configured to be physically inserted into the second receptacle connector, the plug is configured not to be physically inserted into the power supply connector, an insertion port of the first receptacle connector is arranged along a first connector surface, and an insertion port of the second receptacle connector is arranged along a second connector surface.
    Type: Application
    Filed: August 29, 2022
    Publication date: March 2, 2023
    Inventor: Takeshi HARADA
  • Publication number: 20230068782
    Abstract: There are provided a sheet metal; a substrate having a first surface facing an inner surface of the sheet metal; a first receptacle connector having a first part which is in contact with the first surface, and a second part facing the first part, and configured to be coupled to a first plug via a first opening of the sheet metal; and a first prevention section that is coupled to the sheet metal, presses the second part, and prevents the first receptacle connector from peeling off from the first surface.
    Type: Application
    Filed: August 30, 2022
    Publication date: March 2, 2023
    Inventor: Takeshi HARADA
  • Patent number: 11575832
    Abstract: There is realized an imaging device that monitors a communication status or the like, and executes switching processing from an MSC mode to a PTP mode in a case where a pre-defined condition is satisfied. There is provided a control unit configured to execute switching processing between a PTP communication mode applied with a PTP protocol, and an MSC mode, which is a communication mode according to a mass storage class (MSC). For example, in a case where MSC mode communication processing has not been executed for a specified time or more, a case where a movement indicating start of image capturing is detected, or the like, the control unit executes switching processing from the MSC mode to the PTP mode. After switching to the PTP mode, it is possible to execute imaging by inputting an image capturing control command from a host device.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: February 7, 2023
    Assignee: Sony Group Corporation
    Inventors: Takeshi Harada, Ryunosuke Oda
  • Publication number: 20230015582
    Abstract: A chip singulation method includes, in stated order: forming a surface supporting layer on an upper surface of a wafer; thinning the wafer from the undersurface to reduce the thickness to at most 30 ?m; removing the surface supporting layer from the upper surface; forming a first metal layer and subsequently a second metal layer on the undersurface of the wafer; applying a dicing tape onto an undersurface of the second metal layer; applying, onto the upper surface of the wafer, a process of increasing hydrophilicity of a surface of the wafer; forming a water-soluble protective layer on the surface of the wafer; cutting the wafer, the first metal layer, and the second metal layer by irradiating a predetermined region of the upper surface of the wafer with a laser beam; and removing the water-soluble protective layer from the surface of the wafer using wash water.
    Type: Application
    Filed: September 22, 2022
    Publication date: January 19, 2023
    Inventors: Takeshi HARADA, Hiroaki OHTA, Yoshihiro MATSUSHIMA
  • Patent number: 11488867
    Abstract: A chip singulation method includes, in stated order: forming a surface supporting layer on an upper surface of a wafer; thinning the wafer from the undersurface to reduce the thickness to at most 30 ?m; removing the surface supporting layer from the upper surface; forming a first metal layer and subsequently a second metal layer on the undersurface of the wafer; applying a dicing tape onto an undersurface of the second metal layer; applying, onto the upper surface of the wafer, a process of increasing hydrophilicity of a surface of the wafer; forming a water-soluble protective layer on the surface of the wafer; cutting the wafer, the first metal layer, and the second metal layer by irradiating a predetermined region of the upper surface of the wafer with a laser beam; and removing the water-soluble protective layer from the surface of the wafer using wash water.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: November 1, 2022
    Assignee: NUVOTON TECHNOLOGY CORPORATION JAPAN
    Inventors: Takeshi Harada, Hiroaki Ohta, Yoshihiro Matsushima
  • Publication number: 20220343573
    Abstract: An image processing apparatus includes: a moving object extraction unit configured to generate, regarding a moving object extraction target image, an extracted image obtained by extracting an image of a moving object in an area other than a mask area set as an area from which an image to be used for synthesis is not extracted; and an image synthesis unit configured to perform processing of synthesizing the extracted image with another image.
    Type: Application
    Filed: September 9, 2020
    Publication date: October 27, 2022
    Inventors: TAKESHI HARADA, NOBUYOSHI SHIRAI, HIROYOSHI FUJII
  • Publication number: 20220238378
    Abstract: A chip singulation method includes, in stated order: forming a surface supporting layer on an upper surface of a wafer; thinning the wafer from the undersurface to reduce the thickness to at most 30 ?m; removing the surface supporting layer from the upper surface; forming a first metal layer and subsequently a second metal layer on the undersurface of the wafer; applying a dicing tape onto an undersurface of the second metal layer; applying, onto the upper surface of the wafer, a process of increasing hydrophilicity of a surface of the wafer; forming a water-soluble protective layer on the surface of the wafer; cutting the wafer, the first metal layer, and the second metal layer by irradiating a predetermined region of the upper surface of the wafer with a laser beam; and removing the water-soluble protective layer from the surface of the wafer using wash water.
    Type: Application
    Filed: April 18, 2022
    Publication date: July 28, 2022
    Inventors: Takeshi HARADA, Hiroaki OHTA, Yoshihiro MATSUSHIMA
  • Publication number: 20220059651
    Abstract: A semiconductor device that is a chip-size-package-type semiconductor device that is facedown mountable includes: a semiconductor layer including a semiconductor substrate and a low-concentration impurity layer in contact with an upper surface of the semiconductor substrate; a metal layer having a thickness of at least 10 ?m; a first vertical MOS transistor in the semiconductor layer; and a second vertical MOS transistor in the semiconductor layer. A side surface of the metal layer includes roughness forming vertical stripes in a direction perpendicular to the metal layer, and has a maximum height of profile greater than 1.0 ?m. In a plan view of the semiconductor device, an area occupancy of a formation containing metal in the metal layer is at most 5% in a 10-?m square region located at least 13 ?m inward from an outer edge of the semiconductor device, within an upper surface of the semiconductor device.
    Type: Application
    Filed: November 1, 2021
    Publication date: February 24, 2022
    Inventors: Yoshihiro MATSUSHIMA, Yoshihiko KAWAKAMI, Shinya ODA, Takeshi HARADA
  • Patent number: 11257918
    Abstract: A semiconductor device includes a substrate; a first nitride semiconductor layer above the substrate; a second nitride semiconductor layer on the first nitride semiconductor layer; an ohmic electrode above the substrate; and a contact layer in contact with at least a part of the ohmic electrode, the contact layer containing silicon and chlorine. The second nitride semiconductor layer has a wider band gap than the first nitride semiconductor layer. A two-dimensional electron gas channel is formed in the first nitride semiconductor layer at a heterointerface between the first nitride semiconductor layer and the second nitride semiconductor layer. A silicon concentration has a higher peak value than a chlorine concentration in the contact layer.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: February 22, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yusuke Kanda, Hideyuki Okita, Manabu Yanagihara, Takeshi Harada
  • Publication number: 20220013633
    Abstract: A semiconductor device that is a chip-size-package-type semiconductor device that is facedown mountable includes: a semiconductor layer including a semiconductor substrate and a low-concentration impurity layer in contact with an upper surface of the semiconductor substrate; a metal layer having a thickness of at least 10 ?m; a first vertical MOS transistor in the semiconductor layer; and a second vertical MOS transistor in the semiconductor layer. A side surface of the metal layer includes roughness forming vertical stripes in a direction perpendicular to the metal layer, and has a maximum height of profile greater than 1.0 ?m. In a plan view of the semiconductor device, an area occupancy of a formation containing metal in the metal layer is at most 5% in a 10-?m square region located at least 13 ?m inward from an outer edge of the semiconductor device, within an upper surface of the semiconductor device.
    Type: Application
    Filed: August 11, 2021
    Publication date: January 13, 2022
    Inventors: Yoshihiro MATSUSHIMA, Yoshihiko KAWAKAMI, Shinya ODA, Takeshi HARADA
  • Publication number: 20210324462
    Abstract: This disclosure provides a biochip comprising a plurality of wells. The biochip includes a membrane that is disposed in or adjacent to an individual well of the plurality of wells. The membrane comprises a nanopore, and the individual well comprises an electrode that detects a signal upon ionic flow through the pore in response to a species passing through or adjacent to the nanopore. The electrode can be a non-sacrificial electrode. A lipid bilayer can be formed over the plurality of wells using a bubble.
    Type: Application
    Filed: April 27, 2021
    Publication date: October 21, 2021
    Applicant: Roche Sequencing Solutions, Inc.
    Inventors: Randall W. DAVIS, Edward Shian LIU, Eric Takeshi HARADA, Anne AGUIRRE, Andrew TRANS, James POLLARD, Cynthia CECH
  • Publication number: 20210302409
    Abstract: Systems and methods for inserting a single pore into a membrane are described herein. A stepped or ramped voltage waveform can be applied across the membranes of the cells of an array, where the voltage waveform starts at first voltage and increases in magnitude over a period of time to a second voltage. The first voltage is selected to be low enough to reduce the risk of damaging the membrane, while the rate of voltage increase is selected to provide sufficient time for the pores to insert into the membranes. Once a pore is inserted into the membrane, the voltage across the membrane rapidly drops, thereby reducing the risk of damaging the membrane even if the applied voltage between the electrodes is further increased.
    Type: Application
    Filed: June 10, 2021
    Publication date: September 30, 2021
    Inventors: Geoffrey Barrall, George John Carman, Takeshi Harada, Jason Komadina, J. William Maney, JR., Charlotte Yang
  • Patent number: 11061412
    Abstract: An information processing device that operates in an imaging device mounted on a mobile unit, and notifies the mobile unit of failed imaging, when imaging performed by the imaging device has failed.
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: July 13, 2021
    Assignee: SONY CORPORATION
    Inventors: Takeshi Harada, Ryunosuke Oda
  • Patent number: 11021745
    Abstract: This disclosure provides a biochip comprising a plurality of wells. The biochip includes a membrane that is disposed in or adjacent to an individual well of the plurality of wells. The membrane comprises a nanopore, and the individual well comprises an electrode that detects a signal upon ionic flow through the pore in response to a species passing through or adjacent to the nanopore. The electrode can be a non-sacrificial electrode. A lipid bilayer can be formed over the plurality of wells using a bubble.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: June 1, 2021
    Assignee: Roche Sequencing Solutions, Inc.
    Inventors: Randall W. Davis, Edward Shian Liu, Eric Takeshi Harada, Anne Aguirre, Andrew Trans, James Pollard, Cynthia Cech