Patents by Inventor Takeshi Ishiguro
Takeshi Ishiguro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9461109Abstract: A method of forming a superjunction device includes providing a semiconductor layer having first and second opposing main surfaces and a first doping concentration of a dopant of a first conductivity type, forming at least one device proximate the first main surface, forming at least one trench adjacent to the device and extending into the semiconductor layer from the first main surface, doping at least a portion of a sidewall of the trench with a dopant of a second, different conductivity type to form a first region in the semiconductor layer adjacent to the sidewall and extending at least partially between the first and second main surfaces, providing a substrate with a first dielectric layer arranged thereon, bonding the first dielectric layer to the first main surface to cover the trench and at least a portion of the device, and removing the substrate.Type: GrantFiled: June 26, 2015Date of Patent: October 4, 2016Assignee: Icemos Technology, Ltd.Inventors: Takeshi Ishiguro, Samuel Anderson
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Publication number: 20160268367Abstract: A method of forming a superjunction device includes providing a semiconductor layer having first and second opposing main surfaces and a first doping concentration of a dopant of a first conductivity type, forming at least one device proximate the first main surface, forming at least one trench adjacent to the device and extending into the semiconductor layer from the first main surface, doping at least a portion of a sidewall of the trench with a dopant of a second, different conductivity type to form a first region in the semiconductor layer adjacent to the sidewall and extending at least partially between the first and second main surfaces, providing a substrate with a first dielectric layer arranged thereon, bonding the first dielectric layer to the first main surface to cover the trench and at least a portion of the device, and removing the substrate.Type: ApplicationFiled: June 26, 2015Publication date: September 15, 2016Inventors: Takeshi ISHIGURO, Samuel ANDERSON
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Publication number: 20160163787Abstract: A semiconductor chip includes a semiconductor layer having first and second opposing main surfaces. A plurality of MOSFET cells are at least partially formed in the semiconductor layer. A gate pad region is at least partially formed in the semiconductor layer and includes a gate pad contact and a first plurality of trenches extending from the first main surface. The first plurality of trenches are spaced apart from one another in a direction parallel to the first main surface by about 45 micrometers to about 60 micrometers. At least one gate feed region is at least partially formed in the semiconductor layer and includes a gate feed contact and a second plurality of trenches extending from the first main surface. The second plurality of trenches are spaced apart from one another in the direction parallel to the first main surface by about 45 micrometers to about 60 micrometers.Type: ApplicationFiled: February 12, 2016Publication date: June 9, 2016Inventors: Kenji SUGIURA, Takeshi ISHIGURO
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Patent number: 9349725Abstract: A semiconductor device includes a semiconductor layer having first and second main surfaces, with the first surface defining a plane containing first and second perpendicular axes. A first gate is disposed proximate the first main surface and extends parallel to the first axis. A dielectric layer is formed on the first main surface and separates the first gate from the first main surface. First and second trenches are formed in the semiconductor layer proximate the first gate and spaced apart in a direction parallel to the first axis. First and second pluralities of contact windows are formed in the dielectric layer to expose the first main surface and are respectively arranged in first and second rows extending between the first and second trenches in a direction parallel to the first axis. Adjacent contact windows in each first row are separated only by the dielectric layer.Type: GrantFiled: March 13, 2014Date of Patent: May 24, 2016Inventors: Kenji Sugiura, Takeshi Ishiguro
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Patent number: 9147751Abstract: Superjunction semiconductor devices having narrow surface layout of terminal structures and methods of manufacturing the devices are provided. The narrow surface layout of terminal structures is achieved, in part, by connecting a source electrode to a body contact region within a semiconductor substrate at a body contact interface comprising at least a first side of the body contact region other than a portion of a first main surface of the semiconductor substrate.Type: GrantFiled: December 23, 2014Date of Patent: September 29, 2015Assignee: Icemos Technology LtdInventors: Samuel Anderson, Takeshi Ishiguro
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Publication number: 20150111354Abstract: Superjunction semiconductor devices having narrow surface layout of terminal structures and methods of manufacturing the devices are provided. The narrow surface layout of terminal structures is achieved, in part, by connecting a source electrode to a body contact region within a semiconductor substrate at a body contact interface comprising at least a first side of the body contact region other than a portion of a first main surface of the semiconductor substrate.Type: ApplicationFiled: December 23, 2014Publication date: April 23, 2015Inventors: Samuel ANDERSON, Takeshi ISHIGURO
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Patent number: 8963239Abstract: A superjunction device includes a substrate having first and second main surfaces and a first doping concentration of a first dopant. A first semiconductor layer having a second doping concentration of the first dopant is formed on the substrate. A second semiconductor layer is formed on the first layer and has a main surface. At least one trench extends from the main surface at least partially into the first semiconductor layer. A first region having a third doping concentration of the first dopant extends at least partially between the main surface and the first layer. A second region having a fourth doping concentration of a second dopant is disposed between the first region and a trench sidewall and extends at least partially between the main surface and the first layer. A third region having a fifth doping concentration of the first dopant is disposed proximate the main surface.Type: GrantFiled: March 12, 2014Date of Patent: February 24, 2015Assignee: Icemos Technology, Ltd.Inventors: Samuel Anderson, Takeshi Ishiguro, Kenji Sugiura
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Patent number: 8946814Abstract: Superjunction semiconductor devices having narrow surface layout of terminal structures and methods of manufacturing the devices are provided. The narrow surface layout of terminal structures is achieved, in part, by connecting a source electrode to a body contact region within a semiconductor substrate at a body contact interface comprising at least a first side of the body contact region other than a portion of a first main surface of the semiconductor substrate.Type: GrantFiled: April 5, 2013Date of Patent: February 3, 2015Assignee: Icemos Technology Ltd.Inventors: Samuel Anderson, Takeshi Ishiguro
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Publication number: 20140264620Abstract: A semiconductor device includes a semiconductor layer having first and second main surfaces, with the first surface defining a plane containing first and second perpendicular axes. A first gate is disposed proximate the first main surface and extends parallel to the first axis. A dielectric layer is formed on the first main surface and separates the first gate from the first main surface. First and second trenches are formed in the semiconductor layer proximate the first gate and spaced apart in a direction parallel to the first axis. First and second pluralities of contact windows are formed in the dielectric layer to expose the first main surface and are respectively arranged in first and second rows extending between the first and second trenches in a direction parallel to the first axis. Adjacent contact windows in each first row are separated only by the dielectric layer.Type: ApplicationFiled: March 13, 2014Publication date: September 18, 2014Applicant: Icemos Technology Ltd.Inventors: Kenji SUGIURA, Takeshi ISHIGURO
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Publication number: 20140264582Abstract: A superjunction device includes a substrate having first and second main surfaces and a first doping concentration of a first dopant. A first semiconductor layer having a second doping concentration of the first dopant is formed on the substrate. A second semiconductor layer is formed on the first layer and has a main surface. At least one trench extends from the main surface at least partially into the first semiconductor layer. A first region having a third doping concentration of the first dopant extends at least partially between the main surface and the first layer. A second region having a fourth doping concentration of a second dopant is disposed between the first region and a trench sidewall and extends at least partially between the main surface and the first layer. A third region having a fifth doping concentration of the first dopant is disposed proximate the main surface.Type: ApplicationFiled: March 12, 2014Publication date: September 18, 2014Applicant: ICEMOS TECHNOLOGY LTD.Inventors: Samuel ANDERSON, Takeshi ISHIGURO, Kenji SUGIURA
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Publication number: 20140264619Abstract: A semiconductor chip includes a semiconductor layer having first and second opposing main surfaces. A plurality of MOSFET cells are at least partially formed in the semiconductor layer. A gate pad region is at least partially formed in the semiconductor layer and includes a gate pad contact and a first plurality of trenches extending from the first main surface. The first plurality of trenches are spaced apart from one another in a direction parallel to the first main surface by about 45 micrometers to about 60 micrometers. At least one gate feed region is at least partially formed in the semiconductor layer and includes a gate feed contact and a second plurality of trenches extending from the first main surface. The second plurality of trenches are spaced apart from one another in the direction parallel to the first main surface by about 45 micrometers to about 60 micrometers.Type: ApplicationFiled: March 13, 2014Publication date: September 18, 2014Applicant: Michael W. ShoreInventors: Kenji SUGIURA, Takeshi ISHIGURO
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Patent number: 8580651Abstract: Methods for manufacturing trench type semiconductor devices involve refilling the trenches after high temperature processing steps are performed. The methods allow thermally unstable materials to be used as refill materials for the trenches of the device. Trench type semiconductor devices containing thermally unstable refill materials are also provided. In particular, methods of manufacturing and devices of a trench type semiconductor devices containing organic refill materials are provided.Type: GrantFiled: December 21, 2007Date of Patent: November 12, 2013Assignee: Icemos Technology Ltd.Inventor: Takeshi Ishiguro
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Patent number: 8158004Abstract: Provided is a method of manufacturing target substances with use of supercritical fluid chromatography, by which the following are achieved: solution of a problem at the time of sequential injections of samples containing the target substances; an increase of a treatment amount of separation per unit time; and improvement of efficiency in separation. The method includes the steps of: injecting the sample containing the target substances into a mobile phase; and returning composition of the mobile phase to a pre-change state after changing the composition of the mobile phase. The step of returning the composition of the mobile phase to the pre-change state after changing the composition of the mobile phase is performed during a period of time from detection of a peak of one of the target substances which is eluted latest from a column among the target substances separated by the supercritical fluid chromatography apparatus to injection of the next sample, whereby the problem is solved.Type: GrantFiled: October 22, 2009Date of Patent: April 17, 2012Assignee: Daicel Chemical Industries, Ltd.Inventors: Kenichiro Miyazawa, Takeshi Ishiguro
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Patent number: 8114751Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor wafer and forming at least one first trench in the wafer having first and second sidewalls and a first orientation on the wafer. The first sidewall of the at least one first trench is implanted with a dopant of a first conductivity at a first implantation direction. The first sidewall of the at least one first trench is implanted with the dopant of the first conductivity at a second implantation direction. The second implantation direction is orthogonal to the first implantation direction. The first and second implantation directions are non-orthogonal to the first sidewall.Type: GrantFiled: October 28, 2010Date of Patent: February 14, 2012Assignee: Icemos Technology Ltd.Inventors: Takeshi Ishiguro, Hugh J. Griffin, Kenji Sugiura
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Publication number: 20120006750Abstract: Provided is a method of manufacturing target substances with use of supercritical fluid chromatography, by which the following are achieved: solution of a problem at the time of sequential injections of samples containing the target substances; an increase of a treatment amount of separation per unit time; and improvement of efficiency in separation. The method includes the steps of: injecting the sample containing the target substances into a mobile phase; and returning composition of the mobile phase to a pre-change state after changing the composition of the mobile phase. The step of returning the composition of the mobile phase to the pre-change state after changing the composition of the mobile phase is performed during a period of time from detection of a peak of one of the target substances which is eluted latest from a column among the target substances separated by the supercritical fluid chromatography apparatus to injection of the next sample, whereby the problem is solved.Type: ApplicationFiled: October 22, 2009Publication date: January 12, 2012Inventors: Kenichiro Miyazawa, Takeshi Ishiguro
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Publication number: 20110254137Abstract: A method of manufacturing a superjunction device includes providing a semiconductor wafer having at least one die. At least one first trench having a first orientation is formed in the at least one die. At least one second trench having a second orientation that is different from the first orientation is formed in the at least one die.Type: ApplicationFiled: June 27, 2011Publication date: October 20, 2011Inventors: Takeshi Ishiguro, Kenji Sugiura, Hugh J. Griffin
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Patent number: 8041850Abstract: A channel control unit of a storage apparatus is provided with: a variable-length DMA (Direct Memory Access) that performs data transfer of variable-length data sent to or received from the host computer in accordance with an I/O request; a fixed-length DMA that performs data transfer of fixed-length data to and from the cache memory; and a buffer intervening between the variable-length DMA and the fixed-length DMA. In performing the data transfer of the fixed-length data to the cache memory, the fixed-length DMA divides the variable-length data into multiple sets of the fixed-length data each having a data size equivalent to a unit size of data managed in the cache memory, and adds a first integrity code to the last fixed-length data set of the fixed-length data sets generated by the division, the first integrity code being generated based on the entire variable-length data.Type: GrantFiled: February 19, 2009Date of Patent: October 18, 2011Assignee: Hitachi, Ltd.Inventors: Shinichi Kasahara, Osamu Torigoe, Tetsuya Kojima, Takeshi Ishiguro
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Patent number: 8012806Abstract: A method of manufacturing a superjunction device includes providing a semiconductor wafer having at least one die. At least one first trench having a first orientation is formed in the at least one die. At least one second trench having a second orientation that is different from the first orientation is formed in the at least one die.Type: GrantFiled: February 15, 2008Date of Patent: September 6, 2011Assignee: Icemos Technology Ltd.Inventors: Takeshi Ishiguro, Kenji Sugiura, Hugh J. Griffin
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Publication number: 20110068440Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor wafer and forming at least one first trench in the wafer having first and second sidewalls and a first orientation on the wafer. The first sidewall of the at least one first trench is implanted with a dopant of a first conductivity at a first implantation direction. The first sidewall of the at least one first trench is implanted with the dopant of the first conductivity at a second implantation direction. The second implantation direction is orthogonal to the first implantation direction. The first and second implantation directions are non-orthogonal to the first sidewall.Type: ApplicationFiled: October 28, 2010Publication date: March 24, 2011Applicant: Icemos Technology Ltd.Inventors: Takeshi Ishiguro, Hugh J. Griffin, Kenji Sugiura
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Patent number: 7846821Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor wafer and forming at least one first trench in the wafer having first and second sidewalls and a first orientation on the wafer. The first sidewall of the at least one first trench is implanted with a dopant of a first conductivity at a first implantation direction. The first sidewall of the at least one first trench is implanted with the dopant of the first conductivity at a second implantation direction. The second implantation direction is orthogonal to the first implantation direction. The first and second implantation directions are non-orthogonal to the first sidewall.Type: GrantFiled: February 13, 2009Date of Patent: December 7, 2010Assignee: Icemos Technology Ltd.Inventors: Takeshi Ishiguro, Hugh J. Griffin, Kenji Sugiura