Patents by Inventor Takeshi Ishizaki

Takeshi Ishizaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220212995
    Abstract: Provided is an additive for concrete in which viscosity of a cement composition is low and fluidity is high at an initial stage of casting even when the additive is added, and long-term strength of concrete or the like improves by the addition. A cement additive comprising a water-absorbent resin, wherein the water-absorbent resin is formed by polymerizing a monomer mixture containing no less than 50 mol % of a nonionic non-crosslinkable monomer and no less than 0.1 mol % of a nonionic crosslinkable monomer, and a content of an anionic monomer in the monomer mixture is no more than 20 mol %.
    Type: Application
    Filed: March 24, 2020
    Publication date: July 7, 2022
    Inventors: Takeshi TAKAYAMA, Kunihiko ISHIZAKI, Shigeru SAKAMOTO
  • Patent number: 11296109
    Abstract: A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: April 5, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Ryohei Kitao, Atsuko Sakata, Takeshi Ishizaki, Satoshi Wakatsuki, Shinichi Nakao, Shunsuke Ochiai, Kei Watanabe
  • Patent number: 10892300
    Abstract: A storage device according to embodiments includes a first conductive layer; a second conductive layer; a resistance change element provided between the first conductive layer and the second conductive layer; and an intermediate layer provided in any one of a position between the resistance change element and the first conductive layer and a position between the resistance change element and the second conductive layer, the intermediate layer containing at least one element of silicon (Si) and germanium (Ge), tellurium (Te), and aluminum (Al).
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: January 12, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Takanori Usami, Takeshi Ishizaki, Ryohei Kitao, Katsuyoshi Komatsu, Takeshi Iwasaki, Atsuko Sakata
  • Publication number: 20200286954
    Abstract: A storage device according to embodiments includes a first conductive layer; a second conductive layer; a resistance change element provided between the first conductive layer and the second conductive layer; and an intermediate layer provided in any one of a position between the resistance change element and the first conductive layer and a position between the resistance change element and the second conductive layer, the intermediate layer containing at least one element of silicon (Si) and germanium (Ge), tellurium (Te), and aluminum (Al).
    Type: Application
    Filed: September 13, 2019
    Publication date: September 10, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Takanori USAMI, Takeshi ISHIZAKI, Ryohei KITAO, Katsuyoshi KOMATSU, Takeshi IWASAKI, Atsuko SAKATA
  • Patent number: 10727277
    Abstract: A storage device includes a first conductor, a resistance variable film, and a second conductor. The resistance variable film includes a first layer and a second layer. The second layer is located on a side opposite to the first conductor with respect to the first layer, contains oxygen, and has conductivity higher than that of the first layer. The second conductor includes a first portion and a second portion. The first portion abuts on the second layer of the resistance variable film. The second portion is separated from the resistance variable film as compared to the first portion. The oxygen content of the first portion is higher than that of the second portion.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: July 28, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yosuke Murakami, Takeshi Ishizaki, Yusuke Arayashiki, Kazuhiko Yamamoto, Kana Hirayama
  • Patent number: 10700272
    Abstract: According to one embodiment, the semiconductor memory device includes a first electrode, a first material layer, including a first material, located on the first electrode, a second material, surrounded by the first material of the first material layer, including a phase change material, and a second electrode provided on the first material.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: June 30, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuhiro Katono, Takeshi Ishizaki, Atsuko Sakata
  • Publication number: 20200127007
    Abstract: A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Ryohei KITAO, Atsuko SAKATA, Takeshi ISHIZAKI, Satoshi WAKATSUKI, Shinichi NAKAO, Shunsuke OCHIAI, Kei WATANABE
  • Publication number: 20200083295
    Abstract: A storage device includes a first conductor, a resistance variable film, and a second conductor. The resistance variable film includes a first layer and a second layer. The second layer is located on a side opposite to the first conductor with respect to the first layer, contains oxygen, and has conductivity higher than that of the first layer. The second conductor includes a first portion and a second portion. The first portion abuts on the second layer of the resistance variable film. The second portion is separated from the resistance variable film as compared to the first portion. The oxygen content of the first portion is higher than that of the second portion.
    Type: Application
    Filed: February 19, 2019
    Publication date: March 12, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Yosuke MURAKAMI, Takeshi ISHIZAKI, Yusuke ARAYASHIKI, Kazuhiko YAMAMOTO, Kana HIRAYAMA
  • Patent number: 10566280
    Abstract: In one embodiment, a semiconductor device includes a first insulator. The device further includes a metal layer that includes a first metal layer provided on a surface of the first insulator, and a second metal layer provided on a surface of the first metal layer and containing a first metallic element and oxygen or containing aluminum and nitrogen, or includes a third metal layer provided on the surface of the first insulator and containing a second metallic element, aluminum and nitrogen. The device further includes an interconnect material layer provided on a surface of the metal layer.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: February 18, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi Wakatsuki, Masayuki Kitamura, Takeshi Ishizaki, Hiroshi Itokawa, Daisuke Ikeno, Kei Watanabe, Atsuko Sakata
  • Patent number: 10541250
    Abstract: A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: January 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Ryohei Kitao, Atsuko Sakata, Takeshi Ishizaki, Satoshi Wakatsuki, Shinichi Nakao, Shunsuke Ochiai, Kei Watanabe
  • Publication number: 20190279932
    Abstract: In one embodiment, a semiconductor device includes a first insulator. The device further includes a metal layer that includes a first metal layer provided on a surface of the first insulator, and a second metal layer provided on a surface of the first metal layer and containing a first metallic element and oxygen or containing aluminum and nitrogen, or includes a third metal layer provided on the surface of the first insulator and containing a second metallic element, aluminum and nitrogen. The device further includes an interconnect material layer provided on a surface of the metal layer.
    Type: Application
    Filed: August 14, 2018
    Publication date: September 12, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Satoshi WAKATSUKI, Masayuki KITAMURA, Takeshi ISHIZAKI, Hiroshi ITOKAWA, Daisuke IKENO, Kei WATANABE, Atsuko SAKATA
  • Publication number: 20190267543
    Abstract: According to one embodiment, the semiconductor memory device includes a first electrode, a first material layer, comprising a first material, located on the first electrode, a second material, surrounded by the first material of the first material layer, comprising a phase change material, and a second electrode provided on the first material.
    Type: Application
    Filed: August 30, 2018
    Publication date: August 29, 2019
    Inventors: Kazuhiro KATONO, Takeshi ISHIZAKI, Atsuko SAKATA
  • Patent number: 10170494
    Abstract: According to one embodiment, a semiconductor device includes an underlying metal film and a metal film. The underlying metal film is a tantalum-aluminum film having an aluminum content of more than 50 atomic % and less than 85 atomic %, a tungsten-zirconium film having a zirconium content of less than 40 atomic %, a tungsten-titanium film having a titanium content of less than 80 atomic %, or a tungsten film. The metal film is provided on the underlying metal film and in contact with the underlying metal film. The metal film contains at least one of tungsten and molybdenum, and has a main orientation of (100) or (111).
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: January 1, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Takeshi Ishizaki, Atsuko Sakata, Satoshi Wakatsuki
  • Patent number: 9911753
    Abstract: According to one embodiment, an insulating layer is provided above a stairstep portion of a stacked body. A first cover film is provided between the stairstep portion and the insulating layer. The first cover film is of a material different from the insulating layer. A separation portion divides the stacked body and the insulating layer. A second cover film is provided at a side surface of the insulating layer on the separation portion side. The second cover film is of a material different from the insulating layer.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: March 6, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Masayuki Kitamura, Atsuko Sakata, Satoshi Wakatsuki, Takeshi Ishizaki, Daisuke Ikeno, Tomotaka Ariga
  • Patent number: 9905462
    Abstract: According to one embodiment, the stacked body includes a plurality of metal films, a plurality of silicon oxide films, and a plurality of intermediate films. The intermediate films are provided between the metal films and the silicon oxide films. The intermediate films contain silicon nitride. Nitrogen composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the metal films than on sides of interfaces between the intermediate films and the silicon oxide films. Silicon composition ratios of the intermediate films are higher on sides of interfaces between the intermediate films and the silicon oxide films than on sides of interfaces between the intermediate films and the metal films.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: February 27, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Atsuko Sakata, Takeshi Ishizaki, Shinya Okuda, Kei Watanabe, Masayuki Kitamura, Satoshi Wakatsuki, Daisuke Ikeno, Junichi Wada, Hirotaka Ogihara
  • Patent number: 9780111
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a stacked body, a film having semi-conductivity or conductivity, and a memory film. The stacked body includes a plurality of metal layers, a plurality of insulating layers, and a plurality of intermediate layers stacked on a major surface of the substrate. The film extends in the stacked body in a stacking direction of the stacked body. The memory film is provided between the film and the metal layers. The metal layers are tungsten layers and the intermediate layers are tungsten nitride layers. Or the metal layers are molybdenum layers and the intermediate layers are molybdenum nitride layers.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: October 3, 2017
    Assignee: Toshiba Memory Corporation
    Inventors: Takeshi Ishizaki, Junichi Wada, Atsuko Sakata, Kei Watanabe, Masayuki Kitamura, Daisuke Ikeno, Satoshi Wakatsuki, Hirotaka Ogihara, Shinya Okuda
  • Patent number: 9779978
    Abstract: A method of manufacturing a semiconductor device uses a semiconductor manufacturing apparatus including a turn table allowing placement of at least first and second semiconductor substrates and being capable of moving positions of the first and the second semiconductor substrates by turning, a first film forming chamber, and a second film forming chamber. The first and the second film forming chambers are provided with an opening capable of loading and unloading the first and the second semiconductor substrates by lifting and lowering the first and the second semiconductor substrates placed on the turn table. The method includes transferring the first and the second semiconductor substrates between the first and the second film forming chambers by turning the turn fable and lifting and lowering the first and the second semiconductor substrates placed on the turn table; and forming a stack of films above the first and the second semiconductor substrates.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: October 3, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Kei Watanabe, Junichi Wada, Masayuki Kitamura, Takeshi Ishizaki, Shinya Okuda, Hirotaka Ogihara, Satoshi Wakatsuki, Daisuke Ikeno
  • Publication number: 20170186766
    Abstract: A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.
    Type: Application
    Filed: June 28, 2016
    Publication date: June 29, 2017
    Inventors: Ryohei KITAO, Atsuko Sakata, Takeshi Ishizaki, Satoshi Wakatsuki, Shinichi Nakao, Shunsuke Ochiai, Kei Watanabe
  • Patent number: 9673217
    Abstract: According to one embodiment, a semiconductor device includes a stacked body, a semiconductor body, and a stacked film. The stacked body includes a plurality of tungsten layers and a plurality of alloy layers of tungsten and molybdenum. At least portions of the tungsten layers are stacked with an air gap interposed. The alloy layers are provided on surfaces of the tungsten layers opposing the air gap. The semiconductor body extends in a stacking direction through the stacked body. The stacked film is provided between the semiconductor body and the tungsten layers. The stacked film includes a charge storage portion.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: June 6, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Yohei Sato, Yasuhito Yoshimizu, Satoshi Wakatsuki, Takeshi Ishizaki, Masayuki Kitamura, Daisuke Ikeno, Tomotaka Ariga, Junichi Wada, Hiroshi Tomita, Hisashi Okuchi, Ryohei Kitao, Toshiyuki Sasaki, Kazuhito Furumoto
  • Publication number: 20170062466
    Abstract: According to one embodiment, a semiconductor device includes an underlying metal film and a metal film. The underlying metal film is a tantalum-aluminum film having an aluminum content of more than 50 atomic % and less than 85 atomic %, a tungsten-zirconium film having a zirconium content of less than 40 atomic %, a tungsten-titanium film having a titanium content of less than 80 atomic %, or a tungsten film. The metal film is provided on the underlying metal film and in contact with the underlying metal film. The metal film contains at least one of tungsten and molybdenum, and has a main orientation of (100) or (111).
    Type: Application
    Filed: February 19, 2016
    Publication date: March 2, 2017
    Inventors: TAKESHI ISHIZAKI, ATSUKO SAKATA, SATOSHI WAKATSUKI