Abstract: The present invention provides a non-volatile memory capable of realizing erase/write operations in sufficiently small division units while suppressing an increase in chip area to the minimum, and shortening an erase time. Two of a physical erase state and a logical erase state are provided as threshold voltage distribution states of each memory cell. In the logical erase state, a threshold voltage criterion of the memory cell is shifted to a state higher than the physical erase state. When data rewriting of the memory cell placed in the physical erase state is performed, a logical erase is performed and the threshold voltage criterion is shifted to a high voltage level. The logical erase simply shifts the voltage level of the threshold voltage criterion. Since an electrical charge accumulated in the memory cell is not moved, erasing can be done at high speed and in a short period of time.

Abstract: The present invention provides a non-volatile memory capable of realizing erase/write operations in sufficiently small division units while suppressing an increase in chip area to the minimum, and shortening an erase time. Two of a physical erase state and a logical erase state are provided as threshold voltage distribution states of each memory cell. In the logical erase state, a threshold voltage criterion of the memory cell is shifted to a state higher than the physical erase state. When data rewriting of the memory cell placed in the physical erase state is performed, a logical erase is performed and the threshold voltage criterion is shifted to a high voltage level. The logical erase simply shifts the voltage level of the threshold voltage criterion. Since an electrical charge accumulated in the memory cell is not moved, erasing can be done at high speed and in a short period of time.

Abstract: The present invention provides a non-volatile memory capable of realizing erase/write operations in sufficiently small division units while suppressing an increase in chip area to the minimum, and shortening an erase time. Two of a physical erase state and a logical erase state are provided as threshold voltage distribution states of each memory cell. In the logical erase state, a threshold voltage criterion of the memory cell is shifted to a state higher than the physical erase state. When data rewriting of the memory cell placed in the physical erase state is performed, a logical erase is performed and the threshold voltage criterion is shifted to a high voltage level. The logical erase simply shifts the voltage level of the threshold voltage criterion. Since an electrical charge accumulated in the memory cell is not moved, erasing can be done at high speed and in a short period of time.

Abstract: In a flash memory, after an initial write operation ends, each bit line associated with a memory cell subjected to a write is precharged and each bit line associated with a memory cell that is not subjected to the write is discharged and verified to detect a memory cell low in threshold voltage and a memory cell thus detected is subjected to an additional write. The verification can be verified without being affected by a current flowing through the memory cell that is not subjected to the write. All memory cells can have their respective threshold voltages set accurately.

Abstract: In a flash memory, after an initial write operation ends, each bit line associated with a memory cell subjected to a write is precharged and each bit line associated with a memory cell that is not subjected to the write is discharged and verified to detect a memory cell low in threshold voltage and a memory cell thus detected is subjected to an additional write. The verification can be verified without being affected by a current flowing through the memory cell that is not subjected to the write. All memory cells can have their respective threshold voltages set accurately.

Abstract: In a flash memory, after an initial write operation ends, each bit line associated with a memory cell subjected to a write is precharged and each bit line associated with a memory cell that is not subjected to the write is discharged and verified to detect a memory cell low in threshold voltage and a memory cell thus detected is subjected to an additional write. The verification can be verified without being affected by a current flowing through the memory cell that is not subjected to the write. All memory cells can have their respective threshold voltages set accurately.

Abstract: Comparison circuits are provided, corresponding to a plurality of pull up transistors, each for comparing a voltage at an output node and each respective reference voltage different in voltage level from other, and for adjusting a drive current of a corresponding output pull up transistor, and further comparison circuits are provided, corresponding to a plurality of pull down transistors, each for comparing the voltage of the output node and each respective reference voltage different in voltage level from other, and each for adjusting an amount of a drive current of a corresponding pull down transistor in accordance with a result of comparison. The reference voltages each are set to a voltage level between a power supply voltage and a ground voltage. Without a dedicated power supply pin terminal, a signal of a small amplitude having the amplitude limited stably and precisely can be output at high speed.

Abstract: An input circuit in a DRAM includes a differential amplifier circuit amplifying a potential difference between a potential of an input signal and a reference potential, an inverter outputting an inversion signal of an output signal of the differential amplifier circuit, a latch circuit holding an output signal in a preceding cycle, and two resistive elements for switching the reference potential in accordance with an output signal of the latch circuit. Thus, the reference potential is switched in accordance with the logic level of the input signal in the preceding cycle, allowing accurate determination of the logic level of the input signal.

Abstract: An input circuit in a DRAM includes a differential amplifier circuit amplifying a potential difference between a potential of an input signal and a reference potential, an inverter outputting an inversion signal of an output signal of the differential amplifier circuit, a latch circuit holding an output signal in a preceding cycle, and two resistive elements for switching the reference potential in accordance with an output signal of the latch circuit. Thus, the reference potential is switched in accordance with the logic level of the input signal in the preceding cycle, allowing accurate determination of the logic level of the input signal.

Abstract: The position information indicating the position of a memory relative to a controller is stored in a position information generating circuit, and the transfer timing of write data transmitted from an input circuit to a write circuit and the activation timing of a latch transfer instructing signal are adjusted according to this position information. Thus, the semiconductor memory device is provided that is capable of taking in and generating the internal write data reliably even when the flight time of a data bus becomes substantially the same as the cycle time of a clock signal.

Abstract: An external voltage is supplied to a power terminal of a semiconductor chip and is applied to a semiconductor circuit and a regulator circuit. An output control signal is supplied from semiconductor circuit to an output circuit. According to an RD signal output from semiconductor circuit, regulator circuit applies an output voltage obtained by decreasing external voltage to output circuit, thereby enabling power source noise caused in association with the operation of output circuit to be absorbed by regulator circuit without adding an external power terminal dedicated to output circuit.

Abstract: A swivel type working vehicle having a turntable (3) with a rear hood (28) covering an engine (11) and a side hood (42) covering hydraulic equipment. The rear hood (28) includes a pivot device (30) disposed in an upper front end region thereof and having a pivot axis extending transversely of a vehicle body. The rear hood is pivotable by the pivot device between a closed position covering the engine and an open position exposing the engine. The side hood (42) includes a pivot mechanism (50) disposed in a lower front end region thereof and having a pivot axis extending transversely of the vehicle body. The side hood being pivotable by the pivot mechanism between a closed position covering the hydraulic equipment and an open position exposing the hydraulic equipment.

Abstract: A swivel type working vehicle having a turntable (3) with a rear hood (28) covering an engine (11) and a side hood (42) covering hydraulic equipment. The rear hood (28) includes a pivot device (30) disposed in an upper front end region thereof and having a pivot axis extending transversely of a vehicle body. The rear hood is pivotable by the pivot device between a dosed position covering the engine and an open position exposing the engine. The side hood (42) includes a pivot mechanism (50) disposed in a lower front end region thereof and having a pivot axis extending transversely of the vehicle body. The side hood being pivotable by the pivot mechanism between a dosed position covering the hydraulic equipment and an open position exposing the hydraulic equipment.

Abstract: An external voltage is supplied to a power terminal of a semiconductor chip and is applied to a semiconductor circuit and a regulator circuit. An output control signal is supplied from semiconductor circuit to an output circuit. According to an RD signal output from semiconductor circuit, regulator circuit applies an output voltage obtained by decreasing external voltage to output circuit, thereby enabling power source noise caused in association with the operation of output circuit to be absorbed by regulator circuit without adding an external power terminal dedicated to output circuit.

Abstract: The position information indicating the position of a memory relative to a controller is stored in a position information generating circuit, and the transfer timing of write data transmitted from an input circuit to a write circuit and the activation timing of a latch transfer instructing signal are adjusted according to this position information. Thus, the semiconductor memory device is provided that is capable of taking in and generating the internal write data reliably even when the flight time of a data bus becomes substantially the same as the cycle time of a clock signal.

Abstract: Comparison circuits are provided, corresponding to a plurality of pull up transistors, each for comparing a voltage at an output node and each respective reference voltage different in voltage level from other, and for adjusting a drive current of a corresponding output pull up transistor, and further comparison circuits are provided, corresponding to a plurality of pull down transistors, each for comparing the voltage of the output node and each respective reference voltage different in voltage level from other, and each for adjusting an amount of a drive current of a corresponding pull down transistor in accordance with a result of comparison. The reference voltages each are set to a voltage level between a power supply voltage and a ground voltage. Without a dedicated power supply pin terminal, a signal of a small amplitude having the amplitude limited stably and precisely can be output at high speed.

Abstract: An SDRAM is provided with a delay circuit for delaying for a certain time period a signal that attains an active level in response to an active command, and a latch circuit for latching an output signal of the delay circuit and generating a column decoder activating signal every time a level of an internal clock signal changes. Thus, the column decoder activating signal is caused to attain the active level 1.5 clock cycles after the input of the active command so as to start a column-related operation so that the wasteful standby time can be shortened. Thus, a higher speed data read/write operation can be achieved.

Abstract: A synchronous semiconductor memory device capable of improving substantial transfer rate is provided. In response to a write command immediately following an act command, a control signal generating circuit applies an inactive enable signal to a read preamplifier & write buffer. In response to a write command and a precharge command, the control signal generating circuit generates an active enable signal, and the read preamplifier & write buffer writes the data stored in an FIFO to a memory cell. As late write is not performed upon reception of a write command immediately following an act command, erroneous writing of data to a not intended address can be prevented.

Abstract: Memory arrays are divided into banks which can be operated independent from each other. Read data storing registers and write data storing registers operating independent from each other are provided for the banks. The memory array is divided into a plurality of small array blocks, local IO lines are arranged corresponding to each array block, and the local IO lines are connected to global IO lines. The global IO lines are connected to preamplifier groups and to write buffer groups. By control signal generating circuits and by a register control circuit, inhibition of writing of a desired bit only during successive writing operation can be done, data can be collectively written to the selected memory cells when the final data is input if the data writing should be stopped before reaching the wrap length in successive writing, and the timing for activating the memory array when the write cycle should be repeatedly carried out can be delayed.