Abstract: A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.

Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

Abstract: A semiconductor memory device according to an embodiment comprises: a plurality of memory cells; a word line; a plurality of first bit lines and a plurality of second bit lines; and a control circuit. The control circuit is capable of executing: a determining operation that determines whether the memory cell which is to be a write-target includes an erase-target cell whose threshold voltage is to be the erase state, or not; and an inverting operation that inverts selection or unselection of the bit line connected to one of the two memory cells adjacent to the erase-target cell, in the first write operation and the second write operation.

Abstract: A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.

Abstract: A semiconductor device including semiconductor substrate having an active region and an element isolation region, the active region isolated by the element isolation region, the element isolation region provided with an element isolation trench; a memory-cell transistor formed above the semiconductor substrate and having a gate electrode formed above the active region via a first insulating film, the gate electrode formed of a stack including a floating gate electrode, a first interelectrode insulating film, and a control gate electrode; an element isolation insulating film filled in the element isolation trench; and a second interelectrode insulating film disposed above the element isolation insulating film so as to form a stack of the second interelectrode insulating film and the control electrode above the element isolation insulating and a dielectric constant of the second interelectrode insulating film being higher than a dielectric constant of the first interelectrode insulating film.

Abstract: A semiconductor memory device according to an embodiment comprises: a floating gate formed on a substrate via a tunnel insulating film; a gate electrode formed in a region including a region above the floating gate; and an inter-layer insulating film formed between the floating gate and the gate electrode, above and on a side of the floating gate. At least a part of a surface of the floating gate exposed to an inter-layer insulating film side has a silicide layer formed thereon.

Abstract: A semiconductor memory device according to an embodiment comprises: a plurality of memory cells; a word line; a plurality of first bit lines and a plurality of second bit lines; and a control circuit. The control circuit is capable of executing: a determining operation that determines whether the memory cell which is to be a write-target includes an erase-target cell whose threshold voltage is to be the erase state, or not; and an inverting operation that inverts selection or unselection of the bit line connected to one of the two memory cells adjacent to the erase-target cell, in the first write operation and the second write operation.

Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.

Abstract: A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.

Abstract: A device isolation film has a first height in a first area and a second height higher than the first height in a second area. The first area includes a first end of a dummy memory transistor facing a memory string and a part of a device isolation film adjacent thereof. The second area includes a second end of the dummy memory transistor facing a select transistor and a part of the device isolation film adjacent thereof.

Abstract: A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array that includes NAND cell units; and a write/erase circuit configured to execute a select gate write operation, the select gate write operation executing a programming operation for setting a threshold voltage of a drain side select gate and a verify operation for judging whether said threshold voltage has reached a certain value, and, when it is judged by the verify operation on the drain side select gate that the threshold voltage of the drain side select gate has not reached the certain value, repeatedly executing a programming operation for setting a threshold voltage of a drain side dummy cell connected to the drain side select gate and a verify operation for judging whether said threshold voltage has reached a certain value, until the threshold voltage of the drain side dummy cell has reached the certain value.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array that includes NAND cell units; and a write/erase circuit configured to execute a select gate write operation, the select gate write operation executing a programming operation for setting a threshold voltage of a drain side select gate and a verify operation for judging whether said threshold voltage has reached a certain value, and, when it is judged by the verify operation on the drain side select gate that the threshold voltage of the drain side select gate has not reached the certain value, repeatedly executing a programming operation for setting a threshold voltage of a drain side dummy cell connected to the drain side select gate and a verify operation for judging whether said threshold voltage has reached a certain value, until the threshold voltage of the drain side dummy cell has reached the certain value.

Abstract: Word lines extend in a first direction and are commonly connected to memory cells in a plurality of NAND cell units. Bit lines extend in a second direction crossing to the first direction and connected to one ends of the NAND cell units. In one block, both a first and a second NAND cell unit are connected to one of the bit lines. A bit-line-side select transistor in the first NAND cell unit and a source-line-side select transistor in the second NAND cell unit are disposed adjacently to each other. The source-line-side select transistor in the first NAND cell unit and the bit-line-side select transistor in the second NAND cell unit are disposed adjacently to each other.

Abstract: A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.

Abstract: A nonvolatile semiconductor memory device according to an embodiment includes a memory cell array that includes NAND cell units; and a write/erase circuit configured to execute a select gate write operation, the select gate write operation executing a programming operation for setting a threshold voltage of a drain side select gate and a verify operation for judging whether said threshold voltage has reached a certain value, and, when it is judged by the verify operation on the drain side select gate that the threshold voltage of the drain side select gate has not reached the certain value, repeatedly executing a programming operation for setting a threshold voltage of a drain side dummy cell connected to the drain side select gate and a verify operation for judging whether said threshold voltage has reached a certain value, until the threshold voltage of the drain side dummy cell has reached the certain value.

Abstract: Word lines extend in a first direction and are commonly connected to memory cells in a plurality of NAND cell units. Bit lines extend in a second direction crossing to the first direction and connected to one ends of the NAND cell units. In one block, both a first and a second NAND cell unit are connected to one of the bit lines. A bit-line-side select transistor in the first NAND cell unit and a source-line-side select transistor in the second NAND cell unit are disposed adjacently to each other. The source-line-side select transistor in the first NAND cell unit and the bit-line-side select transistor in the second NAND cell unit are disposed adjacently to each other.

Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

Abstract: A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.