Patents by Inventor Takeshi Kamigaichi
Takeshi Kamigaichi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120241910Abstract: A semiconductor memory device includes a semiconductor substrate, a plurality of element isolations, a plurality of first stacked bodies, a second stacked body, and an interlayer insulating film. Distance between each of the first stacked bodies and the second stacked body is longer than distance between adjacent ones of the first stacked bodies. A first void is formed in the interlayer insulating film between the first stacked bodies. A second void is formed in the interlayer insulating film between one of the first stacked bodies and the second stacked body. And, a lower end of the second void is located above a lower end of the first void.Type: ApplicationFiled: September 16, 2011Publication date: September 27, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Jun OGI, Takeshi Kamigaichi, Tatsuo Izumi
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Publication number: 20120235222Abstract: A device isolation film has a first height in a first area and a second height higher than the first height in a second area. The first area includes a first end of a dummy memory transistor facing a memory string and a part of a device isolation film adjacent thereof. The second area includes a second end of the dummy memory transistor facing a select transistor and a part of the device isolation film adjacent thereof.Type: ApplicationFiled: September 20, 2011Publication date: September 20, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Takeshi KAMIGAICHI
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Patent number: 8270220Abstract: A nonvolatile semiconductor storage device includes a memory cell array and a peripheral circuit. The memory cell array includes active areas extending in a first direction, a dummy active area extending in the first direction, memory cells on the plurality of active areas, first dummy cells on the dummy active area, diffusion layer areas each connected to the corresponding memory cell and the corresponding first dummy cell, first contacts in the respective active areas, and a second contact in the dummy active area. The peripheral circuit includes a voltage applying unit configured to apply to each of the first contacts a first voltage to set each of the memory cells in a write enable state or a second voltage to set the memory cells in a write inhibit state, and to apply to the second contact a third voltage to change a threshold of the dummy cell.Type: GrantFiled: March 23, 2010Date of Patent: September 18, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiro Shiino, Atsuhiro Sato, Takeshi Kamigaichi
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Patent number: 8270212Abstract: According to one embodiment, a semiconductor memory device includes first and second upper-layer contact members. The upper-layer contact members are arranged alternately with the first upper-layer contact members in a first direction and shifted in a second direction orthogonal to the first direction. Plugs are formed on the second upper-layer contact members. First metal wirings are provided on the first upper-layer contact members. Second metal wirings are provided on the plugs. A height of a top surface of the plugs is higher than a top surface of the first metal wirings. A width of a bottom surface of the first metal wirings in a shorter-side direction is shorter than a width of a top surface of the first metal wirings. A width of a bottom surface of the second metal wirings in a shorter-side direction is shorter than a width of a top surface of the second metal wirings.Type: GrantFiled: October 22, 2010Date of Patent: September 18, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Izumi, Takeshi Kamigaichi
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Patent number: 8253188Abstract: A semiconductor storage device includes a semiconductor substrate, a first insulator, a laminated insulator including a second insulator having fixed charges more than those of the first insulator, a single-layer insulator, memory cells between the semiconductor substrate and the first insulator, each memory cells separated from an adjacent memory cell by a cavity portion and including a tunnel insulator, a charge accumulation layer, an insulator, and a control gate electrode, a first selection gate transistor between the semiconductor substrate and the first insulator, a second selection gate transistor between the semiconductor substrate and the first insulator, between one memory cell and the first selection gate transistor, and in contact with the laminated insulator on a first side face on a memory cell side thereof, and a high-voltage peripheral circuit transistor between the semiconductor substrate and the first insulator, and in contact with the single-layer insulator on a side face thereof.Type: GrantFiled: March 22, 2010Date of Patent: August 28, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Kamigaichi, Satoshi Nagashima, Kenji Aoyama
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Patent number: 8237218Abstract: A nonvolatile semiconductor memory device includes a first stack unit with a first selection transistor and a second selection transistor formed on a semiconductor substrate and a second stack unit with first insulating layers and first conductive layers stacked alternately on the upper surface of the first stack unit. The second stack unit includes a second insulating layer formed in contact with side walls of the first insulating layer and the first conductive layer, a charge storage layer formed in contact with the second insulating layer for storing electrical charges, a third insulating layer formed in contact with the charge storage layer, and a first semiconductor layer formed in contact with the third insulating layer so as to extend in a stacking direction, with one end connected to one diffusion layer of the first selection transistor and the other end connected to a diffusion layer of the second selection transistor.Type: GrantFiled: September 6, 2011Date of Patent: August 7, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Murata, Takeshi Kamigaichi
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Publication number: 20120198297Abstract: A control circuit performs a write operation to 1-page memory cells along the selected word line, by applying a write pulse voltage to a selected word line, and then performs a verify read operation of confirming whether the data write is completed. When the data write is not completed, a step-up operation is performed of raising the write pulse voltage by a certain step-up voltage. A bit scan circuit determines whether the number of memory cells determined to reach a certain threshold voltage is equal to or more than a certain number among the memory cells read at the same time, according to read data held in the sense amplifier circuit as a result of the verify read operation. The control circuit changes the amount of the step-up voltage according to the determination of the bit scan circuit.Type: ApplicationFiled: September 20, 2011Publication date: August 2, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takeshi KAMIGAICHI, Kenji Sawamura
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Publication number: 20120176839Abstract: A nonvolatile semiconductor memory includes a cell unit having a select gate transistor and a memory cell connected in series, a select gate line connected to the select gate transistor, and a word line connected to the memory cell. One end of the word line is bent to the select gate line side, and a fringe is connected between a bent point and a distal end of the word line.Type: ApplicationFiled: March 22, 2012Publication date: July 12, 2012Inventors: Takeshi Kamigaichi, Takeshi Murata, Itaru Kawabata
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Publication number: 20120168846Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.Type: ApplicationFiled: March 15, 2012Publication date: July 5, 2012Inventors: Michiharu MATSUI, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Takeshi Kamigaichi
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Publication number: 20120163096Abstract: During data read process, a control circuit gives a read voltage to a selected word line connected to a selected memory cell, and gives read pass voltages, for turning on memory cells, to unselected word lines connected to unselected memory cells. The control circuit respectively gives a first read pass voltage, a second read pass voltage, and a third read pass voltage to a first unselected word line adjacent to the selected word line at a side of at least one of a bit line and a source line, a second unselected word line adjacent to the first unselected word line at a side opposite to the selected word line, and a third unselected word line adjacent to the second unselected word line at a side opposite to the selected word line. The second read pass voltage is higher than the third read pass voltage.Type: ApplicationFiled: December 22, 2011Publication date: June 28, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Takuya FUTATSUYAMA, Takeshi Kamigaichi
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Patent number: 8134198Abstract: A nonvolatile semiconductor memory includes active regions . . . AAj?1, AAj, AAj?1, . . . formed in a semiconductor substrate; a plurality of word lines WL0, WL1, . . . in the row direction; memory cell transistors, each including a floating gate provided on the semiconductor substrate via a tunneling insulating film, an inter-gate insulating film disposed on the floating gate, and a control gate disposed on the inter-gate insulating film, disposed on intersections of word lines and active regions; select gate lines SGD in the row direction; bit line contacts CB disposed on the active regions; and a plurality of bit lines in the column direction and connected to the active regions via the bit line contacts; and the bit line contacts are formed by forming an electrode material for the bit line contacts in lines in the row direction and cutting the electrode material for each of the bit lines to avoid contact-failure of bit line contacts CB.Type: GrantFiled: November 24, 2006Date of Patent: March 13, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Kamigaichi, Yasuhiko Matsunaga
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Publication number: 20110316065Abstract: A nonvolatile semiconductor memory device includes a first stack unit with a first selection transistor and a second selection transistor formed on a semiconductor substrate and a second stack unit with first insulating layers and first conductive layers stacked alternately on the upper surface of the first stack unit. The second stack unit includes a second insulating layer formed in contact with side walls of the first insulating layer and the first conductive layer, a charge storage layer formed in contact with the second insulating layer for storing electrical charges, a third insulating layer formed in contact with the charge storage layer, and a first semiconductor layer formed in contact with the third insulating layer so as to extend in a stacking direction, with one end connected to one diffusion layer of the first selection transistor and the other end connected to a diffusion layer of the second selection transistor.Type: ApplicationFiled: September 6, 2011Publication date: December 29, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Takeshi MURATA, Takeshi KAMIGAICHI
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Patent number: 8044448Abstract: A nonvolatile semiconductor memory device includes: a memory cell array region having memory cells connected in series; a control circuit region disposed below the memory cell array region; and an interconnection portion electrically connecting the control circuit region and the memory cell array region. The memory cell array region includes: a plurality of first memory cell regions having the memory cells; and a plurality of connection regions. The interconnection portion is provided in the connection regions. The first memory cell regions are provided at a first pitch in a first direction orthogonal to a lamination direction of the memory cell array region and the control circuit region. The connection regions are provided between the first memory cell regions mutually adjacent in the first direction, and at a second pitch in a second direction orthogonal to the lamination direction and the first direction.Type: GrantFiled: July 24, 2009Date of Patent: October 25, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Kamigaichi, Fumitaka Arai
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Publication number: 20110235413Abstract: A control circuit of a nonvolatile semiconductor memory device according to an embodiment of the present invention sets the lower limit of an intermediate distribution in a page writing operation such that an amount of shift from a first threshold voltage distribution to a second threshold voltage distribution is substantially equal to an amount of shift from the intermediate distribution to a fourth threshold voltage distribution, and raises the lower limit of the intermediate distribution as the number of times writing has been executed increases. When the threshold voltage distribution of a second memory cell adjoining a reading target first memory cell and subject to data write after the first memory cell is the second or fourth threshold voltage distribution, the control circuit executes control of applying a second reading pass voltage higher than the first reading pass voltage to the second memory cell.Type: ApplicationFiled: September 21, 2010Publication date: September 29, 2011Applicant: Kabushiki Kaisha ToshibaInventor: Takeshi KAMIGAICHI
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Publication number: 20110233652Abstract: A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.Type: ApplicationFiled: June 9, 2011Publication date: September 29, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Yasuhiro Shino, Atsuhiro Sato, Takeshi Kamigaichi, Fumitaka Arai
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Patent number: 8026546Abstract: A nonvolatile semiconductor memory device includes a first stack unit with a first selection transistor and a second selection transistor formed on a semiconductor substrate and a second stack unit with first insulating layers and first conductive layers stacked alternately on the upper surface of the first stack unit. The second stack unit includes a second insulating layer formed in contact with side walls of the first insulating layer and the first conductive layer, a charge storage layer formed in contact with the second insulating layer for storing electrical charges, a third insulating layer formed in contact with the charge storage layer, and a first semiconductor layer formed in contact with the third insulating layer so as to extend in a stacking direction, with one end connected to one diffusion layer of the first selection transistor and the other end connected to a diffusion layer of the second selection transistor.Type: GrantFiled: May 1, 2009Date of Patent: September 27, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Murata, Takeshi Kamigaichi
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Publication number: 20110228583Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a first sense amplifier circuit, and a second sense amplifier circuit. The memory cell array includes a plurality of first memory cell units, a plurality of second memory cell units, a plurality of first interconnects, and a plurality of second interconnects. The first sense amplifier circuit is connected to the plurality of first interconnects. The second sense amplifier circuit is connected to the plurality of second interconnects. Heights of upper surfaces of interconnects are equal.Type: ApplicationFiled: February 25, 2011Publication date: September 22, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Mitsuhiro NOGUCHI, Kenji SAWAMURA, Takeshi KAMIGAICHI, Katsuaki ISOBE
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Publication number: 20110193152Abstract: A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.Type: ApplicationFiled: April 14, 2011Publication date: August 11, 2011Inventors: Hiroyuki Kutsukake, Kikuko Sugimae, Takeshi Kamigaichi
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Publication number: 20110186921Abstract: Disclosure is semiconductor device of a selective gate region, comprising a semiconductor layer, a first insulating film formed on the semiconductor layer, a first electrode layer formed on the first insulating layer, an element isolating region comprising an element isolating insulating film formed to extend through the first electrode layer and the first insulating film to reach an inner region of the semiconductor layer, the element isolating region isolating a element region and being self-aligned with the first electrode layer, a second insulating film formed on the first electrode layer and the element isolating region, an open portion exposing a surface of the first electrode layer being formed in the second insulating film, and a second electrode layer formed on the second insulating film and the exposed surface of the first electrode layer, the second electrode layer being electronically connected to the first electrode layer via the open portion.Type: ApplicationFiled: April 13, 2011Publication date: August 4, 2011Inventors: Michiharu MATSUI, Seiichi Mori, Riichiro Shirota, Yuji Takeuchi, Takeshi Kamigaichi
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Patent number: 7977733Abstract: A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.Type: GrantFiled: February 27, 2009Date of Patent: July 12, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiro Shiino, Atsuhiro Sato, Takeshi Kamigaichi, Fumitaka Arai