Patents by Inventor Takeshi Kamino

Takeshi Kamino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9564466
    Abstract: Provided is a semiconductor device with improved performance. The semiconductor device includes a photodiode having a charge storage layer (n-type semiconductor region) and a surface layer (p-type semiconductor region), and a transfer transistor having a gate electrode and a floating diffusion. The surface layer (p-type semiconductor region) of a second conductive type formed over the charge storage layer (n-type semiconductor region) of a first conductive type includes a first sub-region having a low impurity concentration, and a second sub-region having a high impurity concentration. The first sub-region is arranged closer to the floating diffusion than the second sub-region.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: February 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Yotaro Goto
  • Publication number: 20160172419
    Abstract: The performances of a semiconductor device are improved. A semiconductor device has a photodiode and a transfer transistor formed in a pixel region. Further, the semiconductor device has a second transistor formed in a peripheral circuit region. The transfer transistor includes a first gate electrode, and a film part formed of a thick hard mask film formed over the first gate electrode. The second transistor includes a second gate electrode, source/drain regions, silicide layers formed at the upper surface of the second gate electrode, and the upper surfaces of the source/drain regions.
    Type: Application
    Filed: February 22, 2016
    Publication date: June 16, 2016
    Inventor: Takeshi KAMINO
  • Patent number: 9331114
    Abstract: To prevent deterioration in the sensitivity of a pixel part caused by variation in the distance between a waveguide and a photo diode and by decay of light due to suppression of reflection of entering light. In a pixel region, there is formed a waveguide which penetrates through a fourth interlayer insulating film or the like and reaches a sidewall insulating film. The sidewall insulating film is configured to have a stacked structure of a silicon oxide film and a silicon nitride film. The waveguide is formed so as to penetrate through even the silicon nitride film of the sidewall insulating film and to reach the silicon oxide film of the sidewall insulating film, or so as to reach the silicon nitride film of the sidewall.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: May 3, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Takahiro Tomimatsu, Takeshi Kamino, Takeshi Kawamura
  • Publication number: 20160079294
    Abstract: To prevent deterioration in the sensitivity of a pixel part caused by variation in the distance between a waveguide and a photo diode and by decay of light due to suppression of reflection of entering light. In a pixel region, there is formed a waveguide which penetrates through a fourth interlayer insulating film or the like and reaches a sidewall insulating film. The sidewall insulating film is configured to have a stacked structure of a silicon oxide film and a silicon nitride film. The waveguide is formed so as to penetrate through even the silicon nitride film of the sidewall insulating film and to reach the silicon oxide film of the sidewall insulating film, or so as to reach the silicon nitride film of the sidewall.
    Type: Application
    Filed: November 23, 2015
    Publication date: March 17, 2016
    Applicant: Renesas Electronics Corporation
    Inventors: Takahiro TOMIMATSU, Takeshi KAMINO, Takeshi KAWAMURA
  • Publication number: 20160043131
    Abstract: Provided is a semiconductor device with improved performance. The semiconductor device includes a photodiode having a charge storage layer (n-type semiconductor region) and a surface layer (p-type semiconductor region), and a transfer transistor having a gate electrode and a floating diffusion. The surface layer (p-type semiconductor region) of a second conductive type formed over the charge storage layer (n-type semiconductor region) of a first conductive type includes a first sub-region having a low impurity concentration, and a second sub-region having a high impurity concentration. The first sub-region is arranged closer to the floating diffusion than the second sub-region.
    Type: Application
    Filed: July 20, 2015
    Publication date: February 11, 2016
    Inventors: Takeshi Kamino, Yotaro Goto
  • Publication number: 20150303230
    Abstract: An offset spacer film (OSS) is formed on a side wall surface of a gate electrode (NLGE, PLGE) to cover a region in which a photo diode (PD) is disposed. Next, an extension region (LNLD, LPLD) is formed using the offset spacer film and the like as an implantation mask. Next, process is provided to remove the offset spacer film covering the region in which the photo diode is disposed. Next, a sidewall insulating film (SWI) is formed on the side wall surface of the gate electrode. Next, a source-drain region (HPDF, LPDF, HNDF, LNDF) is formed using the sidewall insulating film and the like as an implantation mask.
    Type: Application
    Filed: October 29, 2012
    Publication date: October 22, 2015
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Takeshi Kamino, Takahiro Tomimatsu
  • Publication number: 20150076566
    Abstract: The performances of a semiconductor device are improved. A semiconductor device has a photodiode and a transfer transistor formed in a pixel region. Further, the semiconductor device has a second transistor formed in a peripheral circuit region. The transfer transistor includes a first gate electrode, and a film part formed of a thick hard mask film formed over the first gate electrode. The second transistor includes a second gate electrode, source/drain regions, silicide layers formed at the upper surface of the second gate electrode, and the upper surfaces of the source/drain regions.
    Type: Application
    Filed: September 10, 2014
    Publication date: March 19, 2015
    Inventor: Takeshi KAMINO
  • Publication number: 20140070288
    Abstract: To prevent deterioration in the sensitivity of a pixel part caused by variation in the distance between a waveguide and a photo diode and by decay of light due to suppression of reflection of entering light. In a pixel region, there is formed a waveguide which penetrates through a fourth interlayer insulating film or the like and reaches a sidewall insulating film. The sidewall insulating film is configured to have a stacked structure of a silicon oxide film and a silicon nitride film. The waveguide is formed so as to penetrate through even the silicon nitride film of the sidewall insulating film and to reach the silicon oxide film of the sidewall insulating film, or so as to reach the silicon nitride film of the sidewall.
    Type: Application
    Filed: September 11, 2013
    Publication date: March 13, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Takahiro TOMIMATSU, Takeshi KAMINO, Takeshi KAWAMURA
  • Publication number: 20080272461
    Abstract: There is provided a semiconductor device with a configuration in which a dummy silicide area 11 is provided in the vicinity of a non-silicide area 2 to easily capture residual refractory metals, resulting in an improved yield by preventing the trapping of residual refractory metals into a non-silicide area and thereby reducing a junction leakage within the non-silicide area.
    Type: Application
    Filed: June 26, 2008
    Publication date: November 6, 2008
    Inventors: Takeshi Kamino, Toshiaki Tsutsumi, Shuji Kodama, Takio Ohno
  • Patent number: 7408239
    Abstract: There is provided a semiconductor device with a configuration in which a dummy silicide area 11 is provided in the vicinity of a non-silicide area 2 to easily capture residual refractory metals, resulting in an improved yield by preventing the trapping of residual refractory metals into a non-silicide area and thereby reducing a junction leakage within the non-silicide area.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: August 5, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Takeshi Kamino, Toshiaki Tsutsumi, Shuji Kodama, Takio Ohno
  • Publication number: 20070114666
    Abstract: There is provided a semiconductor device with a configuration in which a dummy silicide area 11 is provided in the vicinity of a non-silicide area 2 to easily capture residual refractory metals, resulting in an improved yield by preventing the trapping of residual refractory metals into a non-silicide area and thereby reducing a junction leakage within the non-silicide area.
    Type: Application
    Filed: January 9, 2007
    Publication date: May 24, 2007
    Inventors: Takeshi Kamino, Toshiaki Tsutsumi, Shuji Kodama, Takio Ohno
  • Patent number: 7180153
    Abstract: There is provided a semiconductor device with a configuration in which a dummy silicide area 11 is provided in the vicinity of a non-silicide area 2 to easily capture residual refractory metals, resulting in an improved yield by preventing the trapping of residual refractory metals into a non-silicide area and thereby reducing a junction leakage within the non-silicide area.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: February 20, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Takeshi Kamino, Toshiaki Tsutsumi, Shuji Kodama, Takio Ohno
  • Publication number: 20020140097
    Abstract: There is provided a semiconductor device with a configuration in which a dummy silicide area 11 is provided in the vicinity of a non-silicide area 2 to easily capture residual refractory metals, resulting in an improved yield by preventing the trapping of residual refractory metals into a non-silicide area and thereby reducing a junction leakage within the non-silicide area.
    Type: Application
    Filed: October 23, 2001
    Publication date: October 3, 2002
    Inventors: Takeshi Kamino, Toshiaki Tsutsumi, Shuji Kodama, Takio Ohno