Abstract: A contact structure is formed with no voids in an interlayer insulation film and good surface planarity. A first insulation film (21) formed of p-TEOS is deposited to cover a substrate (1) and wires (4) formed on the substrate (1). A second insulation film (22) which is coating glass is formed by SOG. The surface is etched back from the opposite side to the substrate (1); therefore, the second insulation film (22) is etched. The etching is stopped at the point where the surface (21a) of the first insulation film (21) on the wires (4) is exposed. This ensures good surface,planarity. A third insulation film (23) is stacked on top of the second insulation film (22), and portions of the third insulation film (23) above the wires (4) are isotropically etched to form openings (51). At this time, the isotropic etching does not extend over the second insulation film (22).

Abstract: Provided is a method of manufacturing a semiconductor device having a capacitor above a semiconductor substrate, with which it is possible to reduce the number of steps and the cost of manufacture. Specifically, a polysilicon layer (12) in which impurity is diffused is deposited on the entire surface including the inside of a hole (8A). An etching process of the polysilicon layer (12) is performed to form a storage node electrode composed of the polysilicon layer (12) remaining on the bottom and side of a groove for metallization (15) and in the hole (8A). The storage node electrode is broadly divided into a storage node electrode body disposed on the bottom and side of the groove for metallization (15), and a plug part disposed in the hole (8A). The storage node electrode is electrically connected via the plug part to a diffused region (19) of a semiconductor substrate (1).

Abstract: There is described the manufacture of a semiconductor device having a storage node or high-yield manufacture of a compact memory IC.

Abstract: A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.

Abstract: A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.

Abstract: Along with an arithmetic processing unit and an arithmetic execution unit, another arithmetic processing unit is coupled in parallel to an instruction issue unit. Disposed within one of the arithmetic processing units are an address generation unit, an instruction buffer, an instruction decoder, an arithmetic execution unit, a data memory, and a flag register. The instruction decoder decodes an instruction read from the instruction buffer. If the decoded instruction is an iteration start instruction, the instruction decoder extracts a number of times an iterative process is to be executed that is included in the instruction for forwarding to the address generation unit. The address generation unit exerts control as to the execution and termination of iterative processes.