Patents by Inventor Takeshi Koshiba
Takeshi Koshiba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230290833Abstract: A manufacturing method of a semiconductor device includes preparing a silicon carbide substrate, growing an epitaxial layer, and forming a structure. The silicon carbide substrate has an upper surface on which an alignment mark having a recessed shape is disposed, and a perpendicular line to the upper surface is inclined with respect to a [0001] direction toward a [11-20] direction. The epitaxial layer is grown on the upper surface and covers the alignment mark. The structure is formed on or above the upper surface at a position apart from the alignment mark by an interval P in the [11-20] direction along the upper surface. The interval P satisfies a relationship of D/tan ? < P < 10D/tan ?, where D is a depth of the alignment mark and ? is an inclination angle of the perpendicular line with respect to the [0001] direction.Type: ApplicationFiled: February 2, 2023Publication date: September 14, 2023Inventors: Hitoshi FUJIOKA, Takeshi KOSHIBA, Norihiro TOGAWA, Takuji ARAUCHI
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Publication number: 20160260643Abstract: According to one embodiment, there is provided a semiconductor device having a mark, the mark including a reference pattern extending in a first direction, a measuring pattern extending in the first direction, and a first stepped portion. The measuring pattern is separated by a predetermined distance in the second direction intersecting the first direction from the reference pattern. The first stepped portion has a level difference of one or more steps and is disposed on side in the second direction of the measuring pattern.Type: ApplicationFiled: September 8, 2015Publication date: September 8, 2016Applicant: Kabushiki Kaisha ToshibaInventor: Takeshi KOSHIBA
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Patent number: 9389513Abstract: In one embodiment, a method of forming a resist pattern on a substrate is provided. Information of a template pattern formed on a template based on template pattern data is obtained. A resist coating distribution is set based on the information of the template pattern. A resist is formed on a substrate based on the resist coating distribution. The template is brought into contact with the resist formed on the substrate so that the resist is filled into the template pattern formed on the template. The filled resist is cured. The template is separated from the cured resist so that a resist pattern is formed on the substrate.Type: GrantFiled: September 10, 2010Date of Patent: July 12, 2016Assignee: Kabushiki Kaisha ToshibaInventor: Takeshi Koshiba
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Patent number: 9381540Abstract: A pattern forming method includes determining an amount of curable resin to be formed on a substrate, the curable resin having volatility, the amount of the curable resin being determined by a calculation considering volatile loss of the curable resin, the calculation being performed for each of a plurality of regions of the substrate, forming the curable resin having the determined amount on the substrate, the forming the curable resin being performed for each of the plurality of regions of the substrate, contacting the curable resin formed on the substrate with a template, the template including a pattern to be filled with the curable resin by the contacting, and curing the curable resin under a condition where the curable resin is in contact with the template.Type: GrantFiled: April 27, 2015Date of Patent: July 5, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Takeshi Koshiba, Ikuo Yoneda, Tetsuro Nakasugi
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Publication number: 20150224536Abstract: A pattern forming method includes determining an amount of curable resin to be formed on a substrate, the curable resin having volatility, the amount of the curable resin being determined by a calculation considering volatile loss of the curable resin, the calculation being performed for each of a plurality of regions of the substrate, forming the curable resin having the determined amount on the substrate, the forming the curable resin being performed for each of the plurality of regions of the substrate, contacting the curable resin formed on the substrate with a template, the template including a pattern to be filled with the curable resin by the contacting, and curing the curable resin under a condition where the curable resin is in contact with the template.Type: ApplicationFiled: April 27, 2015Publication date: August 13, 2015Inventors: Takeshi KOSHIBA, Ikuo YONEDA, Tetsuro NAKASUGI
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Patent number: 9046763Abstract: A pattern forming method includes determining an amount of curable resin to be formed on a substrate, the curable resin having volatility, the amount of the curable resin being determined by a calculation considering volatile loss of the curable resin, the calculation being performed for each of a plurality of regions of the substrate, forming the curable resin having the determined amount on the substrate, the forming the curable resin being performed for each of the plurality of regions of the substrate, contacting the curable resin formed on the substrate with a template, the template including a pattern to be filled with the curable resin by the contacting, and curing the curable resin under a condition where the curable resin is in contact with the template.Type: GrantFiled: March 18, 2010Date of Patent: June 2, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Takeshi Koshiba, Ikuo Yoneda, Tetsuro Nakasugi
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Patent number: 8907346Abstract: An imprint apparatus according to embodiments includes a stage, a dropping unit that drops resist, an imprinting unit that presses a circuit pattern of a template against the resist on a transfer target substrate, an underlying position detecting unit, a correcting unit, and a dropping position control unit. The underlying position detecting unit detects a position of an underlying pattern on the transfer target substrate. The correcting unit corrects a dropping position of the resist on a basis of a position of the underlying pattern. The dropping position control unit causes the resist to be dropped onto a dropping position after correction on the transfer target substrate on the basis of corrected dropping position.Type: GrantFiled: January 11, 2013Date of Patent: December 9, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Koshiba, Nobuhiro Komine
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Publication number: 20140349219Abstract: According to embodiments, an exposure method is provided. In the exposure method, a transmittance of a pellicle is adjusted every position of a mask pattern included in a reflection type mask. And when adjusting the transmittance of the pellicle, a film thickness of the pellicle is adjusted on the basis of a transmittance correction amount. Thereafter, exposure is conducted onto a substrate by using the reflection type mask with the pellicle stuck thereon.Type: ApplicationFiled: November 25, 2013Publication date: November 27, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Hiroyuki MIZUNO, Yosuke Okamoto, Takeshi Koshiba, Satoshi Nagai
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Publication number: 20140319700Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming one or more first patterns and one or more second patterns adjacent to the first patterns on a substrate, each first pattern including a linear portion extending in a first direction, and each second pattern including first and second linear portions extending in the first direction and a connection portion connecting end portions of the first and second linear portions with each other. The method further includes forming a resist layer on the first and second patterns. The method further includes forming a resist opening in the resist layer so that at least a part of a contour line of the resist opening is a curved line and the curved line overlaps the second patterns. The method further includes dividing the second patterns into the first and second linear portions by etching using the resist layer.Type: ApplicationFiled: December 18, 2013Publication date: October 30, 2014Applicant: Kabushiki Kaisha ToshibaInventor: Takeshi KOSHIBA
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Publication number: 20140065735Abstract: An imprint apparatus according to embodiments includes a stage, a dropping unit that drops resist, an imprinting unit that presses a circuit pattern of a template against the resist on a transfer target substrate, an underlying position detecting unit, a correcting unit, and a dropping position control unit. The underlying position detecting unit detects a position of an underlying pattern on the transfer target substrate. The correcting unit corrects a dropping position of the resist on a basis of a position of the underlying pattern. The dropping position control unit causes the resist to be dropped onto a dropping position after correction on the transfer target substrate on the basis of corrected dropping position.Type: ApplicationFiled: January 11, 2013Publication date: March 6, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Takeshi Koshiba, Nobuhiro Komine
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Publication number: 20130220970Abstract: According to one embodiment, a method for fabricating a template, includes providing a mask pattern on a template substrate, processing the template substrate using the mask pattern as a mask so as to provide a first pattern on a first area in the template substrate and a second pattern on a second area which is located adjacent to the first area in the template, providing a first mask material on the template substrate so as to cover the first area, and processing the second area using the first mask material as a mask so as to lower a height of a surface of the second area than a height of a surface of the first area.Type: ApplicationFiled: August 29, 2012Publication date: August 29, 2013Inventor: Takeshi KOSHIBA
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Patent number: 8423926Abstract: According to one embodiment, an acceptance determining method of a blank for an EUV mask includes evaluating whether or not an integrated circuit device becomes defective, on the basis of information of a defect contained in a blank for an EUV mask and design information of a mask pattern to be formed on the blank. The integrated circuit device is to be manufactured by using the EUV mask. The EUV mask is manufactured by forming the mask pattern on the blank. And the blank is determined to be non-defective in a case that the integrated circuit device is not to be defective.Type: GrantFiled: September 20, 2011Date of Patent: April 16, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Takeshi Koshiba, Hidefumi Mukai, Seiro Miyoshi, Kazunori Iida
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Publication number: 20120174045Abstract: According to one embodiment, an acceptance determining method of a blank for an EUV mask includes evaluating whether or not an integrated circuit device becomes defective, on the basis of information of a defect contained in a blank for an EUV mask and design information of a mask pattern to be formed on the blank. The integrated circuit device is to be manufactured by using the EUV mask. The EUV mask is manufactured by forming the mask pattern on the blank. And the blank is determined to be non-defective in a case that the integrated circuit device is not to be defective.Type: ApplicationFiled: September 20, 2011Publication date: July 5, 2012Inventors: Takeshi KOSHIBA, Hidefumi Mukai, Seiro Miyoshi, Kazunori IIda
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Patent number: 8178366Abstract: In the pattern forming method according to the embodiment, second templates are manufactured by an imprint technology using first templates manufactured by applying a predetermined misalignment distribution for each shot on a first substrate by an exposure apparatus. Then, an upper-layer-side pattern is formed by an imprint technology using a second template in which an inter-layer misalignment amount between a lower-layer-side pattern already formed above a second substrate and the upper-layer-side pattern to be formed above the second substrate becomes equal to or lower than a predetermined reference value.Type: GrantFiled: January 27, 2011Date of Patent: May 15, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Seiro Miyoshi, Hidefumi Mukai, Takeshi Koshiba
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Publication number: 20120009791Abstract: According to one embodiment, a pattern formation method is disclosed. The method can include filling an imprint material between a first protrusion-depression pattern of a first pattern transfer layer formed on a first replica substrate and a second pattern transfer layer being transparent to energy radiation and formed on a second replica substrate transparent to the energy radiation. The method can include curing the imprint material by irradiating the imprint material with the energy radiation from an opposite surface side of the second replica substrate. The method can include releasing the first protrusion-depression pattern from the imprint material. The method can include forming a second protrusion-depression pattern in the second pattern transfer layer by processing the second pattern transfer layer using the imprint material as a mask.Type: ApplicationFiled: July 1, 2011Publication date: January 12, 2012Inventors: Yingkang ZHANG, Masafumi Asano, Takeshi Koshiba
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Publication number: 20110300646Abstract: In the pattern forming method according to the embodiment, second templates are manufactured by an imprint technology using first templates manufactured by applying a predetermined misalignment distribution for each shot on a first substrate by an exposure apparatus. Then, an upper-layer-side pattern is formed by an imprint technology using a second template in which an inter-layer misalignment amount between a lower-layer-side pattern already formed above a second substrate and the upper-layer-side pattern to be formed above the second substrate becomes equal to or lower than a predetermined reference value.Type: ApplicationFiled: January 27, 2011Publication date: December 8, 2011Inventors: Seiro MIYOSHI, Hidefumi MUKAI, Takeshi KOSHIBA
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Publication number: 20110194751Abstract: A pattern verification method and the like for forming a desired pattern by using the imprint method are provided. A pattern verification method for a pattern forming method in which a template pattern of a template is transferred to a resist on a substrate to thus form a resist pattern, and the substrate is processed by using the resist pattern as a mask to thus form a processed pattern, the pattern verification method comprises: extracting any one of a design pattern of the processed pattern, a target pattern of the resist pattern, and a target pattern of the template pattern, as a verification pattern; and verifying whether the verification pattern is a critical pattern or not by comparing a feature value of the verification pattern with a feature value of a critical pattern.Type: ApplicationFiled: February 8, 2011Publication date: August 11, 2011Inventors: Michiya TAKIMOTO, Takeshi Koshiba
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Publication number: 20110189601Abstract: In one embodiment, a method of forming a resist pattern on a substrate is provided. Information of a template pattern formed on a template based on template pattern data is obtained. A resist coating distribution is set based on the information of the template pattern. A resist is formed on a substrate based on the resist coating distribution. The template is brought into contact with the resist formed on the substrate so that the resist is filled into the template pattern formed on the template. The filled resist is cured. The template is separated from the cured resist so that a resist pattern is formed on the substrate.Type: ApplicationFiled: September 10, 2010Publication date: August 4, 2011Inventor: Takeshi KOSHIBA
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Patent number: 7985958Abstract: According to an aspect of the invention, there is provided an electron beam drawing apparatus comprising at least one stage of a deflection amplifier and a deflection unit, a first storage section which stores shot information at a drawing time, a second storage section which stores a correction table indicating a relation between the shot information and an output voltage of the deflection amplifier, and an adjusting section which adjusts an output of the deflection amplifier based on the correction table stored in the second storage section and the shot information stored in the first storage section.Type: GrantFiled: November 8, 2005Date of Patent: July 26, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuro Nakasugi, Kazuo Tawarayama, Hiroyuki Mizuno, Takumi Ota, Noriaki Sasaki, Tatsuhiko Higashiki, Takeshi Koshiba, Shunko Magoshi
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Publication number: 20110143271Abstract: A pattern generating method includes obtaining an on-substrate pattern by performing a process for forming the on-substrate pattern by simulation or experiment based on a design pattern of the on-substrate pattern formed by an imprint process using a template, employing the design pattern when a comparison result of the design pattern and obtained on-substrate pattern satisfies a predetermined condition, and correcting the design pattern to satisfy the predetermined condition when the comparison result does not satisfy the predetermined condition.Type: ApplicationFiled: June 24, 2010Publication date: June 16, 2011Inventors: Takeshi KOSHIBA, Hidefumi Mukai, Kazuhito Kobayashi, Takumi Ota