Abstract: The present disclosure relates to a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.

Abstract: The present technology relates to a semiconductor device, a solid-state image pickup element, an imaging device, and an electronic apparatus that can suppress characteristic fluctuations caused by capacitance fluctuations due to a dummy wire, while maintaining an affixing bonding strength by the dummy wire. Two or more chips in which wires that are electrically connected are formed on bonding surfaces and the bonding surfaces opposing each other are bonded to be laminated are included and, with respect to a region where the wires are periodically and repeatedly disposed in sharing units each made up of a plurality of pixels sharing the same floating diffusion contact, a dummy wire is disposed at the center position thereof on the bonding surface at a pitch of the sharing unit. The present technology can be applied to a CMOS image sensor.

Abstract: The present disclosure relates to a stacked device, a manufacturing method, and an electronic instrument, capable of suppressing adverse effects of noise generated from one substrate, onto the other substrate. A first metal layer is formed on a bonding surface of one substrate, and a second metal layer is formed on a bonding surface of the other substrate stacked with the one substrate. Subsequently, an electromagnetic wave shield structure that interrupts an electromagnetic wave between the one substrate and the other substrate is provided by bonding the metal layer of the one substrate with the metal layer of the other substrate and by performing potential fixing. The present technology can be applied, for example, to a stacked CMOS image sensor.

Abstract: A solid-state imaging device includes: a plurality of substrates stacked via a wiring layer or an insulation layer; a light sensing section that is formed in a substrate, of the plurality of substrates, disposed on a light incident side and that generates a signal charge in accordance with an amount of received light; and a contact portion that is connected to a non-light incident-surface side of the substrate in which the light sensing section is formed and that supplies a desired voltage to the substrate from a wire in a wiring layer disposed on a non-light incident side of the substrate.

Abstract: There is provided an image sensor having a plurality of pixels, each pixel including a light receiving portion configured to receive incident light, a waveguide configured to guide the incident light from a light incident surface to the light receiving portion, and a light shielding portion disposed between the light incident surface and the light receiving portion, for blocking the incident light. The light shielding portion has an opening formed near a light emitting surface of the waveguide. The light receiving portion receives the incident light passing through the waveguide and the opening. A width of a core of the waveguide and a width of the opening are set so that the widths increase as a wavelength of the light incident on a pixel becomes longer.

Abstract: A solid-state imaging device includes: a plurality of substrates stacked via a wiring layer or an insulation layer; a light sensing section that is formed in a substrate, of the plurality of substrates, disposed on a light incident side and that generates a signal charge in accordance with an amount of received light; and a contact portion that is connected to a non-light incident-surface side of the substrate in which the light sensing section is formed and that supplies a desired voltage to the substrate from a wire in a wiring layer disposed on a non-light incident side of the substrate.

Abstract: A solid-state imaging device includes: a plurality of substrates stacked via a wiring layer or an insulation layer; a light sensing section that is formed in a substrate, of the plurality of substrates, disposed on a light incident side and that generates a signal charge in accordance with an amount of received light; and a contact portion that is connected to a non-light incident-surface side of the substrate in which the light sensing section is formed and that supplies a desired voltage to the substrate from a wire in a wiring layer disposed on a non-light incident side of the substrate.

Abstract: A photomask includes a base, a plurality of chip pattern regions over which a light shielding pattern of a metal material is defined, the plurality of chip pattern regions being defined on the base, scribe regions defined between the chip pattern regions, the scribe regions being defined by using the light shielding pattern, and slits in which the light shielding pattern is not defined, the slits being defined so as to surround the chip pattern regions.

Abstract: A solid-state imaging device includes: a plurality of substrates stacked via a wiring layer or an insulation layer; a light sensing section that is formed in a substrate, of the plurality of substrates, disposed on a light incident side and that generates a signal charge in accordance with an amount of received light; and a contact portion that is connected to a non-light incident-surface side of the substrate in which the light sensing section is formed and that supplies a desired voltage to the substrate from a wire in a wiring layer disposed on a non-light incident side of the substrate.

Abstract: A photomask includes a base, a plurality of chip pattern regions over which a light shielding pattern of a metal material is defined, the plurality of chip pattern regions being defined on the base, scribe regions defined between the chip pattern regions, the scribe regions being defined by using the light shielding pattern, and slits in which the light shielding pattern is not defined, the slits being defined so as to surround the chip pattern regions.

Abstract: A method of manufacturing a semiconductor device including an interconnection and a capacitor formed with a Cu layer in accordance with the present invention includes the steps of forming an interlayer insulation layer, forming an interconnection hole and a capacitor hole in the interlayer insulation layer, filling the interconnection hole with the Cu layer to form an interconnection layer, and partly filling the capacitor hole with the Cu layer to form one electrode of the capacitor. The step of filling the interconnection hole with the Cu layer to form the interconnection layer and the step of partly filling the capacitor hole with the Cu layer to form one electrode of the capacitor are performed in a single process step. Thus, manufacturing process of the semiconductor device can be simplified.

Abstract: A gate oxide film is formed on a substrate. A polysilicon film is formed on the gate oxide film. A ruthenium film is formed as a mask material on the polysilicon film. A resist pattern is formed on the ruthenium film. After the ruthenium film is patterned using the resist pattern as a mask, a the patterned ruthenium film is shrunk. After the polysilicon film is patterned using a shrunk the shrunken ruthenium film, the shrunk shrunken ruthenium film is removed.

Abstract: A semiconductor device having a capacitor and a method of manufacturing thereof are provided, securing a certain capacitance while allowing the size to be reduced. The semiconductor device includes a capacitor lower electrode having an upper surface and including a metal film, a dielectric film deposited on the upper surface of the capacitor lower electrode and having its thickness smaller than that of the capacitor lower electrode, and a capacitor upper electrode deposited on the dielectric film, having its width smaller than that of the capacitor lower electrode and including a metal film.

Abstract: A semiconductor device having a capacitor and a method of manufacturing thereof are provided, securing a certain capacitance while allowing the size to be reduced. The semiconductor device includes a capacitor lower electrode having an upper surface and including a metal film, a dielectric film deposited on the upper surface of the capacitor lower electrode and having its thickness smaller than that of the capacitor lower electrode, and a capacitor upper electrode deposited on the dielectric film, having its width smaller than that of the capacitor lower electrode and including a metal film.

Abstract: In the production of semiconductor devices, when forming a predetermined pattern within a to-be-processed material such as interlayer film, photoresist is first applied over the material, then exposed, and developed, to thereby form a resist film having the predetermined pattern shape on the material. The material is next etched to a predetermined depth through the resist film as a mask. The resist film is removed and then the material is further etched to form the predetermined pattern within the material. Then, an etching stopper film has been formed at a predetermined depth, the etching is continued until the etching reaches the etching stopper film, and then the photoresist is removed. Additionally, an antireflection layer is used as the etching stopper film.

Abstract: A first photoresist film 36 with low sensitivity and a second photoresist film 38 with high sensitivity are stacked on an interlayer insulating film 14 formed on a semiconductor substrate (FIGS. 1A to 1C). The first and second photoresist films 36 and 38 are exposed simultaneously using a photolithography mask 40 having a first transmittance part 48 corresponding to the contact hole and a second transmittance part 50 corresponding to the upper wiring (FIG. 1D). They are developed so that the difference in depth between the contact hole and the upper wiring is three-dimensionally reflected in the first and second photoresist films 36 and 38 (FIG. 1E). Etching is carried out by using them as a mask to form the contact hole and the upper wiring.

Abstract: A semiconductor device having a capacitor and a method of manufacturing thereof are provided, securing a certain capacitance while allowing the size to be reduced. The semiconductor device includes a capacitor lower electrode having an upper surface and including a metal film, a dielectric film deposited on the upper surface of the capacitor lower electrode and having its thickness smaller than that of the capacitor lower electrode, and a capacitor upper electrode deposited on the dielectric film, having its width smaller than that of the capacitor lower electrode and including a metal film.

Abstract: A first photoresist film 36 with low sensitivity and a second photoresist film 38 with high sensitivity are stacked on an interlayer insulating film 14 formed on a semiconductor substrate (FIGS. 1A to 1C). The first and second photoresist films 36 and 38 are exposed simultaneously using a photolithography mask 40 having a first transmittance part 48 corresponding to the contact hole and a second transmittance part 50 corresponding to the upper wiring (FIG. 1D). They are developed so that the difference in depth between the contact hole and the upper wiring is three-dimensionally reflected in the first and second photoresist films 36 and 38 (FIG. 1E). Etching is carried out by using them as a mask to form the contact hole and the upper wiring.