Abstract: A component-embedded substrate includes a first wiring substrate, an electronic component provided on the first wiring substrate, an intermediate wiring substrate provided around the electronic component on the first wiring substrate and connected to the first wiring substrate via a first connection member, a second wiring substrate provided above the first wiring substrate, the electronic component and the intermediate wiring substrate, and connected to the intermediate wiring substrate via a second connection member, and an encapsulating resin filled between the first wiring substrate and the second wiring substrate and covering the electronic component and the intermediate wiring substrate. Side surfaces of the intermediate wiring substrate are entirely covered by the encapsulating resin.

Abstract: A component-embedded substrate includes a first wiring substrate, an electronic component provided on the first wiring substrate, an intermediate wiring substrate provided around the electronic component on the first wiring substrate and connected to the first wiring substrate via a first connection member, a second wiring substrate provided above the first wiring substrate, the electronic component and the intermediate wiring substrate, and connected to the intermediate wiring substrate via a second connection member, and an encapsulating resin filled between the first wiring substrate and the second wiring substrate and covering the electronic component and the intermediate wiring substrate. Side surfaces of the intermediate wiring substrate are entirely covered by the encapsulating resin.

Abstract: Provided is a technology capable of improving the quality of a GaN layer that is formed on an underlying substrate. A group III-nitride laminated substrate includes an underlying substrate, a first layer that is formed on the underlying substrate and is made of aluminum nitride, and a second layer that is formed on the first layer and is made of gallium nitride. The second layer has a thickness of 10 ?m or less. A half-value width of (0002) diffraction determined through X-ray rocking curve analysis is 100 seconds or less, and a half-value width of (10-12) diffraction determined through X-ray rocking curve analysis is 200 seconds or less.

Abstract: An epitaxial wafer for a heterojunction bipolar transistor and a heterojunction bipolar transistor capable of reducing the resistance of the sub-collector layer without reducing the current amplification factor are provided. In an epitaxial wafer for a heterojunction bipolar transistor including a sub-collector layer made of n-type GaAs, the sub-collector layer contains n-type impurities having a covalent radius that is smaller than the covalent radius of the substitution site and n-type impurities having a covalent radius that is larger than the covalent radius of the substitution site.

Abstract: An epitaxial wafer for a heterojunction bipolar transistor and a heterojunction bipolar transistor capable of reducing the resistance of the sub-collector layer without reducing the current amplification factor are provided. In an epitaxial wafer for a heterojunction bipolar transistor including a sub-collector layer made of n-type GaAs, the sub-collector layer contains n-type impurities having a covalent radius that is smaller than the covalent radius of the substitution site and n-type impurities having a covalent radius that is larger than the covalent radius of the substitution site.

Abstract: An epitaxial wafer for a heterojunction bipolar transistor and a heterojunction bipolar transistor that are capable of further reducing a turn-on voltage are provided. An epitaxial wafer for a heterojunction bipolar transistor includes a collector layer made of GaAs, a base layer formed on the collector layer and made of InGaAs, and an emitter layer formed on the base layer and made of InGaP, and the base layer has an In composition that decreases from the emitter layer side toward the collector layer side.

Abstract: An epitaxial wafer for a heterojunction bipolar transistor and a heterojunction bipolar transistor that are capable of further reducing a turn-on voltage are provided. An epitaxial wafer for a heterojunction bipolar transistor includes a collector layer made of GaAs, a base layer formed on the collector layer and made of InGaAs, and an emitter layer formed on the base layer and made of InGaP, and the base layer has an In composition that decreases from the emitter layer side toward the collector layer side.

Abstract: A nitride semiconductor epitaxial wafer includes a substrate, and a nitride semiconductor layer formed on the substrate, the nitride semiconductor layer including a (002) plane in an upper surface thereof. An in-plane dispersion of a full width half maximum (FWHM) of an X-ray rocking curve in the (002) plane or a (100) plane of the nitride semiconductor layer is not more than 30%. The wafer is not less than 100 ?m in thickness and not less than 50 mm in diameter.

Abstract: A nitride semiconductor epitaxial wafer includes a substrate, and a nitride semiconductor layer formed on the substrate, the nitride semiconductor layer including a (002) plane in an upper surface thereof. An in-plane dispersion of a full width half maximum (FWHM) of an X-ray rocking curve in the (002) plane or a (100) plane of the nitride semiconductor layer is not more than 30%. The wafer is not less than 100 ?m in thickness and not less than 50 mm in diameter.

Abstract: A battery includes: a battery element having a cathode and an anode; a package can containing the battery element and being electrically connected to one of the cathode and the anode; and external connection terminal being connected to the other one of the cathode and the anode; and having a plate-like base contained in the package can and a leading portion extending to outside of the package can; and an insulating member separating the external connection terminal from the battery element. The base of the external connection terminal is spaced from an internal wall face of the package can, and the insulating member has notches at a position where the base of the external connection terminal is layered on the insulating member in the thickness direction of the package can.

Abstract: To provide a transistor device, which is composed of a compound semiconductor, having a multilayer structure in which a high electron mobility transistor (HEMT) and a heterojunction bipolar transistor (HBT) are overlapped on the same substrate and epitaxial-grown thereon, wherein a band gap energy of an indium gallium phosphide layer (InGaP) included in an epitaxial layer, is set to 1.91 eV or more.

Abstract: A battery includes a spirally wound electrode body including a positive electrode and a negative electrode spirally wound, a center pin provided in the hollow portion of the spirally wound electrode body, and an exterior body configured to house the spirally wound electrode body and the center pin. The center pin includes at least one end having a plurality of cut-out portions.

Abstract: A nitride semiconductor free-standing substrate includes a nitride semiconductor crystal and an inversion domain with a density of not less than 10/cm2 and not more than 600/cm2 in a section parallel to a surface of the substrate and inside the substrate. A method for making the nitride semiconductor free-standing substrate includes a nitride semiconductor crystal growth step of growing on a heterosubstrate a nitride semiconductor crystal including an inversion domain with a density of not less than 10/cm2 and not more than 600/cm2 by adjusting a growth condition at an initial growth stage of the nitride semiconductor crystal, and a separation step for separating the grown nitride semiconductor crystal from the heterosubstrate to form the nitride semiconductor free-standing substrate.

Abstract: To provide a transistor device, which is composed of a compound semiconductor, having a multilayer structure in which a high electron mobility transistor (HEMT) and a heterojunction bipolar transistor (HBT) are overlapped on the same substrate and epitaxial-grown thereon, wherein a band gap energy of an indium gallium phosphide layer (InGaP) included in an epitaxial layer, is set to 1.91 eV or more.

Abstract: A nonaqueous electrolyte battery includes an outer case having one open end portion, a battery element held in the outer case, and a battery lid which is disposed on the one open end portion and which is provided with a protrusion portion protruded toward the outside of the battery, at least two opening portions disposed in the protrusion portion, and release portions disposed adjoining the respective opening portions so as to deform in accordance with an increase in internal pressure of the battery.

Abstract: A battery with improved safety that can more surely short-circuit electrodes when flattened out by the external force is provided. A center pin (30) is inserted in the center of a spirally wound electrode body formed by layering and spirally winding a cathode and an anode with a separator in between. The center pin (30) has a cut line (31) provided in the longitudinal direction and a first cutout (32) vertically crossing the cut line (31). When flattened out by the external force, a corner (33) at an intersection of the cut line (31) and the first cutout (32) is projected, and short-circuit is surely generated. Further, it is preferable that the center pin (30) has a second cutout (34) in the direction perpendicular to the cut line (31) in a position facing the cut line (31) in the circumferential direction.

Abstract: To provide a group-III nitride semiconductor freestanding substrate, with carrier concentration of a peripheral part of a n-type group-III nitride semiconductor freestanding substrate set to be lower than the carrier concentration inside of the peripheral part. In this freestanding substrate, preferably value ?? obtained by dividing a difference between a maximum value of the carrier concentration and a minimum value of the carrier concentration in a surface of the freestanding substrate by the maximum value of the carrier concentration is greater than 0.05, and the carrier concentration in any place in the surface of the freestanding substrate exceeds 5.0×1017 cm?3.

Abstract: A nitride semiconductor substrate has a first surface forming a principal surface of the substrate. A first edge is formed by beveling at least a portion of an edge of the first surface of the substrate. A scattering region is formed in at least a portion of the first edge. The scattering region scatters more external incident light than the first surface.

Abstract: A battery with improved safety which can establish a short circuit between electrodes more reliably when the battery is crushed by an external force is provided. A battery includes a battery element including a cathode and an anode, a battery can containing the battery element, and a conductive short circuit member arranged in a gap between the battery element and the battery can, the short circuit member capable of biting into the battery element when the battery can is deformed.

Abstract: A method for manufacturing a nitride semiconductor substrate including the steps of: forming a nitride semiconductor layer on a sapphire substrate, and manufacturing a freestanding nitride semiconductor substrate by using the nitride semiconductor layer separated from the sapphire substrate, wherein variability of inclinations of the C-axes, being a difference between a maximum value and a minimum value of inclination of the C-axes in a radially-outward direction at each point on a front surface of the sapphire substrate is 0.3° or more and 1° or less.